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JP-7857483-B2 - Semiconductor equipment

JP7857483B2JP 7857483 B2JP7857483 B2JP 7857483B2JP-7857483-B2

Inventors

  • 山崎 舜平
  • 小山 潤
  • 今井 馨太郎

Assignees

  • 株式会社半導体エネルギー研究所

Dates

Publication Date
20260512
Application Date
20250909
Priority Date
20091021

Claims (5)

  1. The device comprises a first transistor having silicon in its first channel formation region, and a second transistor having an oxide semiconductor in its second channel formation region. Either the source or the drain of the second transistor is electrically connected to the gate of the first transistor. A semiconductor device in which two or more potentials are input to the gate of the first transistor via the second channel formation region, A first conductive film having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating film having a region positioned above the first conductive film, A second conductive film having a region positioned above the first insulating film and functioning as the gate of the second transistor, A second insulating film having a region positioned above the second conductive film and functioning as a gate insulating film of the second transistor, An oxide semiconductor film having a region positioned above the second insulating film and having the second channel-forming region, A third insulating film having a region positioned above the oxide semiconductor film and a region in contact with the oxide semiconductor film, A fourth insulating film having a region positioned above the third insulating film, A third conductive film having a region positioned above the fourth insulating film, The first conductive film is electrically connected to the oxide semiconductor film via the third conductive film. The first insulating film comprises nitrogen and silicon, The second insulating film has a laminated structure of an insulating film having nitrogen and silicon and an insulating film having oxygen and silicon. The third insulating film comprises oxygen and silicon, The fourth insulating film comprises nitrogen and silicon, A semiconductor device wherein, in a plan view, the first conductive film does not have a region that overlaps with the oxide semiconductor film.
  2. The device comprises a first transistor having silicon in its first channel formation region, and a second transistor having an oxide semiconductor in its second channel formation region. Either the source or the drain of the second transistor is electrically connected to the gate of the first transistor. A semiconductor device in which two or more potentials are input to the gate of the first transistor via the second channel formation region, A first conductive film having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating film having a region positioned above the first conductive film, A second conductive film having a region positioned above the first insulating film and functioning as the gate of the second transistor, A second insulating film having a region positioned above the second conductive film and functioning as a gate insulating film of the second transistor, An oxide semiconductor film having a region positioned above the second insulating film and having the second channel-forming region, A third insulating film having a region positioned above the oxide semiconductor film and a region in contact with the oxide semiconductor film, A fourth insulating film having a region positioned above the third insulating film, A third conductive film having a region positioned above the fourth insulating film, The first conductive film is electrically connected to the oxide semiconductor film via the third conductive film. The first insulating film comprises nitrogen and silicon, The second insulating film has a laminated structure of an insulating film having nitrogen and silicon and an insulating film having oxygen and silicon. The third insulating film comprises oxygen and silicon, The fourth insulating film comprises nitrogen and silicon, In a plan view, the first conductive film does not have a region that overlaps with the oxide semiconductor film. In a plan view, the maximum length of the oxide semiconductor film in the channel length direction of the second transistor is greater than the maximum length of the oxide semiconductor film in the channel width direction of the second transistor. In a plan view, the maximum length of the third conductive film in the channel length direction of the second transistor is greater than the maximum length of the third conductive film in the channel width direction of the second transistor. In a plan view, the maximum length of the first conductive film in the channel width direction of the second transistor is greater than the maximum length of the region in the channel width direction of the second transistor where the third conductive film overlaps with the first conductive film. A semiconductor device wherein, in a plan view, the maximum length of the first conductive film in the channel width direction of the second transistor is greater than the maximum length of the oxide semiconductor film in the channel width direction of the second transistor.
  3. In claim 1 or claim 2, The present invention provides a fourth conductive film having a region located above the fourth insulating film and electrically connected to the silicon semiconductor layer having the first channel-forming region, A constant potential is applied to the fourth conductive film. When the constant potential is applied to either the source or the drain of the first transistor, the potential of the other source or drain of the first transistor is controlled according to the charge held at least at the gate of the first transistor. A semiconductor device wherein the third conductive film and the fourth conductive film have regions in contact with the upper surface of the fourth insulating film.
  4. In any one of claims 1 to 3, A semiconductor device in which, in a plan view, the channel formation region of the first transistor has a region in which current flows in a direction intersecting the channel length direction of the second transistor.
  5. In any one of claims 1 to 4, The second transistor is a semiconductor device having an off-current of 1 × 10⁻¹⁹ A/μm or less.

Description

The technical field of the invention relates to a semiconductor device and a method for manufacturing the same. Here, a semiconductor device is: This term refers to all elements and devices that function by utilizing semiconductor properties. Metal oxides exist in a wide variety of forms and are used in various applications. Indium oxide is a well-known material and is used as a material for transparent electrodes required in liquid crystal display devices and other applications. Some metal oxides exhibit semiconductor properties. Examples of metal oxides exhibiting semiconductor properties include tungsten oxide, tin oxide, indium oxide, and zinc oxide, and thin-film transistors using such metal oxides in the channel formation region are already known (see, for example, Patent Documents 1 to 4, Non-Patent Document 1, etc.). Incidentally, metal oxides include not only monochromatic oxides but also multi-component oxides. For example, InGaO3 (ZnO) m (m: natural number), which has a homologous phase, is known as a multi-component oxide semiconductor containing In, Ga, and Zn (see, for example, Non-Patent Documents 2 to 4). Furthermore, it has been confirmed that oxide semiconductors composed of the above-mentioned In-Ga-Zn-based oxides can also be applied to the channel formation region of thin-film transistors (see, for example, Patent Document 5, Non-Patent Document 5, and Non-Patent Document 6, etc.). Japanese Unexamined Patent Publication No. 198861/1986Japanese Patent Application Publication No. 8-264794Special Publication No. 11-505377Japanese Patent Publication No. 2000-150900Japanese Patent Publication No. 2004-103957 M. W. Prins, K. O. Grosse-Holz, G. Muller, J. F. M. Cillessen, J. B. Giesbers, R. P. Weening, and R. M. Wolf, "A ferroelectric transparent thin-film transistor", Appl. Phys. Lett. , 17 June 1996, Vol. 68 p. 3650-3652M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350°C", J. Solid State Chem. , 1991, Vol. 93, p. 298-315N. Kimizuka, M. Isobe, and M. Nakamura, “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m(m=3,4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m (m=7,8,9, and 16) in the In2O3-ZnGa2O4-ZnO System", J. Solid State Chem. , 1995, Vol. 116, p. 170-178Masaki Nakamura, Noboru Kimizuka, Naohiko Mohri, and Mitsumasa Isobe, "Synthesis and Crystal Structure of Homologous Phase, InFeO3(ZnO)m (m: natural number) and its Isomorphic Compounds," Solid State Physics, 1993, Vol. 28, No. 5, pp. 317-327.K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, "Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor", SCIENCE, 2003, Vol. 300, p. 1269-1272K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide "Semiconductors", NATURE, 2004, Vol. 432 p. 488-492 Cross-sectional and plan views illustrating a semiconductor device.Circuit diagram for explaining semiconductor devicesCross-sectional and plan views illustrating a semiconductor device.Cross-sectional diagram illustrating the manufacturing process of semiconductor devices.Cross-sectional diagram illustrating the manufacturing process of semiconductor devices.Cross-sectional diagram illustrating the manufacturing process of semiconductor devices.Cross-sectional and plan views illustrating a semiconductor device.Circuit diagram for explaining semiconductor devicesCross-sectional and plan views illustrating a semiconductor device.Circuit diagram for explaining semiconductor devicesA diagram illustrating electronic devices using semiconductor devices. An example of an embodiment of the present invention will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the contents of the embodiments shown below. Please note that the location, size, and scope of each component shown in the drawings may not represent the actual location, size, and scope in order to facilitate understanding. Therefore, the actual location, size, and scope are not necessarily limited to those disclosed in the drawings. Furthermore, it should be noted that the ordinal numbers such as "First,""Second," and "Third" used in this specification are added to avoid confusion of the constituent elements and do not imply any numerical limitation. (Embodiment 1) In this embodiment, the configuration and manufacturing method of a semiconductor device according to one aspect of the disclosed invention will be described with reference to Figures 1 to 6. <Configuration of a semiconductor device> Figure 1(