JP-WO2025191975-A5 -

Dates

Publication Date

20260508

Application Date

20241225

Description

The semiconductor device comprises an insulating circuit board 1, semiconductor chips 2a to 2h arranged on the insulating circuit board 1, and a wiring board 3 arranged on the semiconductor chips 2a to 2h. The insulated circuit board 1 is made of, for example, a direct copper bond substrate (DCB substrate), an activated brazed substrate ( AMB substrate), etc. The insulated circuit board 1 has an insulating layer 4, conductive layers 5a to 5c arranged on the upper surface S1 side of the insulating layer 4, and a cooling plate 6 arranged on the lower surface S2 side of the insulating layer 4. The insulating layer 4 is composed of, for example, a ceramic plate mainly composed of aluminum oxide ( Al₂O₃ ), aluminum nitride ( AlN ), silicon nitride ( Si₃N₄ ), boron nitride (BN), etc., or a resin insulating layer using polymer materials, etc. When a resin insulating layer is used as the insulating layer 4, the cooling plate 6 may be omitted. The insulating layer 4 is provided in the shape of a rectangular plate, with its upper surface S1 facing upward. As shown in Figure 2, one end 27 (the inner end; the left end in Figure 2) of the negative electrode terminal 18 in the longitudinal direction is positioned between the insulating circuit board 1 and the wiring board 3, and is joined to the conductive layer 5c of the insulating circuit board 1 via a bonding material 28 such as solder or sintered material. In addition, one end 27, that is, the portion that overlaps with the upper circuit pattern 10b and the lower circuit pattern 11d of the wiring board 3 in a plan view, is provided with a plurality of second through holes (second through holes 22h in Figure 2). The second through holes are provided at positions that overlap with the first through holes 16e to 16h of the wiring board 3 in a plan view. That is, the second through holes of the negative electrode terminal 18 are arranged in series along the width direction of the negative electrode terminal 18. Board-to-board connection pins 24e to 24h (board-to-board connection pin 24h in Figure 2) are press-fitted into the second through holes of the negative electrode terminal 18 (second through holes 22h in Figure 2). Specifically, the lower ends of the inter-board connection pins 24e to 24h are press-fitted into the second through-hole (second through-hole 22h in Figure 2), and the upper ends are press-fitted into the first through-hole (first through-hole 16h in Figure 2), which is located in a position that overlaps with the second through-hole in a plan view. As a result, the wiring board 3 and the negative electrode terminal 18 are integrated via the inter-board connection pins 24e to 24h, and relative movement between the wiring board 3 and the negative electrode terminal 18 is suppressed. Also, because there are two or more inter-board connection pins 24e to 24h, relative rotation between the wiring board 3 and the negative electrode terminal 18 is suppressed. Furthermore, the wiring board 3 and the negative electrode terminal 18 are connected to the insulating circuit board 1 via the inter-board connection pins 24e to 24h , and a heat dissipation path to the cooling plate 6 is provided, suppressing heat buildup inside the semiconductor device. Furthermore, since the negative electrode terminal 18 and the conductive layer 5c are connected via a bonding material 28, the electrical resistance R can be reduced, Joule heat P can be reduced, and heat buildup inside the semiconductor device can be further suppressed. Figure 2 shows, as an example, the configuration around the inter-substrate connection pin 24h among the inter-substrate connection pins 24e to 24h, but the configuration around the other inter-substrate connection pins is similar. Furthermore, the lower ends of the inter-substrate connection pins 24e to 24h pass through the second through-hole of the negative electrode terminal 18 (second through-hole 22h in Figure 2) and are electrically connected to the upper surface of the conductive layer 5c via the bonding material 28 for joining the negative electrode terminal 18. Also, the upper ends of the inter-substrate connection pins 24e to 24h pass through the first through-holes 16e to 16h and are electrically connected to the upper circuit pattern 10b and the lower circuit pattern 11d via the plating layer (see Figure 5; plating layer 54h in Figure 5) provided on the inner surface of the first through-holes 16e to 16h. The upper circuit pattern 10b and the lower circuit pattern 11d are examples of "wiring layers of a wiring board". In Figure 5, the plating layer 54h is continuous with the upper circuit pattern 10b and the lower circuit pattern 11d. As a result, the upper circuit pattern 10b and lower circuit pattern 11d of the wiring board 3 and the conductive layer 5c of the insulating circuit board 1 are electrically connected via the inter-board connection pins 24e to 24h. In other words, the inter-board connection pins 24e to 24h have the functions o