KR-102959980-B1 - APPARATUS FOR TESTING SEMICONDUCTOR

KR102959980B1KR 102959980 B1KR102959980 B1KR 102959980B1KR-102959980-B1

Abstract

A semiconductor test device is provided. A semiconductor test device according to some embodiments, and a semiconductor test device according to one embodiment of the present disclosure for solving the above technical problem, may include a DPS (Device Power Supply) circuit that converts and outputs a first voltage related to the test of a device under test into a second voltage based on a voltage of ground connected to the DPS circuit, and an analog-to-digital converter that converts the second voltage into a digital value based on the difference between the second voltage output from the DPS circuit and the voltage of ground.

Inventors

이동현
조효익
이원길

Assignees

주식회사 와이씨

Dates

Publication Date: 20260511
Application Date: 20240723

Claims (10)

In a semiconductor test device, The DPS circuit that converts and outputs a first voltage related to the test of the device under test into a second voltage based on the voltage of ground connected to the DPS (Device Power Supply) circuit; and It includes an analog-to-digital converter that converts the second voltage into a digital value based on the difference between the second voltage output from the DPS circuit and the voltage of the ground, and The above DPS circuit is, A driver circuit that supplies a signal to the above-mentioned device under test; and A measuring unit comprising a first voltage measuring unit based on a voltage or current generated in a line formed between the above driver circuit and the above device under test, Semiconductor test device.
In paragraph 1, The second voltage is input to the (+) terminal of the analog-to-digital converter, and the ground voltage is input to the (-) terminal of the analog-to-digital converter. Semiconductor test device.
In paragraph 2, A line is formed between the above DPS circuit and the (-) terminal of the above analog-to-digital converter, and The above DPS circuit supplies the voltage of ground to the analog-digital converter through a line formed between the DPS circuit and the (-) terminal of the analog-digital converter, Semiconductor test device.
delete
In paragraph 1, A first line is formed between the above measuring unit and the (+) terminal of the analog-to-digital converter, and A second line is formed between the above measuring unit and the (-) terminal of the analog-to-digital converter, and The above measuring unit supplies the second voltage to the analog-digital converter through the first line and supplies the voltage of ground to the analog-digital converter through the second line. Semiconductor test device.
In a semiconductor test device, The first DPS circuit that converts and outputs a first voltage related to the test of the first device under test into a second voltage based on the voltage of the first ground connected to the first DPS circuit; The second DPS circuit that converts and outputs a third voltage related to the test of the second device under test into a fourth voltage based on the voltage of the second ground connected to the second DPS circuit; A multiplexer that selects and outputs one of the second voltage and the fourth voltage; and An analog-to-digital converter comprising: converting the second voltage to a first digital value based on the difference between the second voltage output from the multiplexer and the voltage of the first ground; and converting the fourth voltage to a second digital value based on the difference between the fourth voltage output from the multiplexer and the voltage of the second ground. Semiconductor test device.
In paragraph 6, The first DPS circuit outputs the voltage of the first ground to the multiplexer, and The second DPS circuit outputs the voltage of the second ground to the multiplexer, and The multiplexer outputs the second voltage and the first ground voltage to the analog-to-digital converter, or outputs the fourth voltage and the second ground voltage to the analog-to-digital converter. Semiconductor test device.
In Paragraph 7, A first line and a second line are formed between the above multiplexer and the above first DPS circuit, and A third line and a fourth line are formed between the above multiplexer and the above second DPS circuit, and The first DPS circuit outputs the second voltage to the multiplexer through the first line and outputs the voltage of the first ground to the multiplexer through the second line, and The second DPS circuit outputs the fourth voltage to the multiplexer through the third line and outputs the voltage of the second ground to the multiplexer through the fourth line. Semiconductor test device.
In paragraph 6, The second voltage or the fourth voltage is input to the (+) terminal of the analog-to-digital converter, and the voltage of the first ground or the voltage of the second ground is input to the (-) terminal of the analog-to-digital converter. Semiconductor test device.
In Paragraph 9, A fifth line is formed between the (-) terminal of the above multiplexer and the above analog-to-digital converter, and The multiplexer supplies the voltage of the first ground or the voltage of the second ground to the analog-to-digital converter through the fifth line. Semiconductor test device.

Description

Semiconductor Test Device {APPARATUS FOR TESTING SEMICONDUCTOR} The present disclosure relates to a semiconductor test device for preventing measurement errors when conducting semiconductor tests. A semiconductor test device is also referred to as an Automatic Test Equipment (ATE), and it is a device that tests whether a device under test (DUT) is a good product by applying an electrical test signal to the device under test and analyzing the response thereto. The semiconductor test device may include a Device Power Supply (DPS) circuit and an Analog Digital Converter (ADC) for supplying power. FIG. 1 is a drawing showing a conventional semiconductor test device (100). Referring to FIG. 1, the driver (112) included in the DPS circuit (110) transmits an electrical test signal to the Device Under Test (DUT) and receives a response signal from the Device Under Test. Additionally, the measuring unit (114) outputs a voltage measured based on the potential of the input first ground (142). Here, the voltage output from the measuring unit (114) is an analog voltage, which is a voltage detected using the driver (112). The analog voltage output from the measurement unit (114) is input to the (+) terminal of the ADC (120), and the ADC (120) converts the analog voltage into a digital value based on the voltage difference between the second ground voltage input to the (-) terminal and the analog voltage input to the (+) terminal. The converted digital value is transmitted to the FPGA (Field Programmable Gate Array) (130). Additionally, the FPGA (130) can proceed with a subsequent process related to determining the quality of the device under test based on the received digital value. Meanwhile, as illustrated in FIG. 1, the positions of each ground (142, 144) in a conventional semiconductor test device (100) may differ. However, as the current output to the device under test increases, the current returned to the second ground (144) may increase, and the voltage of the second ground (144) may fluctuate. In this case, the voltages of each ground (142, 144) within the semiconductor test device (100) are formed differently from each other, and as the voltage of the ground (260) is different, an inaccurate digital value may be transmitted from the ADC (120) to the FPGA (130). In this case, the measurement result for the device under test may become inaccurate. Accordingly, technology is required to minimize errors in the ADC (120) caused by changes in ground voltage. Figure 1 is a drawing showing a conventional semiconductor test device. FIG. 2 is a drawing illustrating a semiconductor test device according to one embodiment of the present disclosure. FIG. 3 is a drawing illustrating a semiconductor test device according to another embodiment of the present disclosure. FIG. 4 is a drawing illustrating a semiconductor test device according to another embodiment of the present disclosure. Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the attached drawings. The advantages and features of the present disclosure and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the attached drawings. However, the technical concept of the present disclosure is not limited to the following embodiments but can be implemented in various different forms. The following embodiments are provided merely to complete the technical concept of the present disclosure and to fully inform those skilled in the art of the scope of the present disclosure, and the technical concept of the present disclosure is defined only by the scope of the claims. It should be noted that when assigning reference numerals to the components of each drawing, the same components are given the same reference numeral whenever possible, even if they are shown in different drawings. Furthermore, in describing the present disclosure, if it is determined that a detailed description of related known components or functions could obscure the essence of the present disclosure, such detailed description is omitted. Unless otherwise defined, all terms used herein (including technical and scientific terms) may be used in a meaning commonly understood by those skilled in the art to which this disclosure pertains. Additionally, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise. The terms used herein are for describing the embodiments and are not intended to limit this disclosure. In this specification, the singular form includes the plural form unless specifically stated otherwise in the text. Additionally, terms such as first, second, A, B, (a), (b), etc., may be used to describe the components of the present disclosure. These terms are intended only to distinguish the components from other components and do not limit the nature, order, or sequence of the components. Wh