KR-102959983-B1 - PIXEL CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME

Abstract

The display device includes a first lower electrode disposed on a base substrate, a first upper electrode disposed on the first lower electrode and overlapping with the first lower electrode, comprising a silicon semiconductor and constituting the first lower electrode and a first capacitor, a second lower electrode disposed on the first upper electrode, and a second upper electrode disposed on the second lower electrode and overlapping with the second lower electrode, comprising an oxide semiconductor and constituting the second lower electrode and a second capacitor.

Inventors

• 김명호
• 김연홍
• 김재범
• 손경석
• 이선희
• 이승준
• 이승헌
• 임준형

Assignees

• 삼성디스플레이 주식회사

Dates

Publication Date

20260507

Application Date

20201201

Claims (20)

1. A first lower electrode disposed on a base substrate; A first upper electrode disposed on the first lower electrode, overlapping with the first lower electrode, comprising a silicon semiconductor, and constituting the first lower electrode and the first capacitor; A second lower electrode disposed on the first upper electrode; A second upper electrode disposed on the second lower electrode, overlapping with the second lower electrode, comprising an oxide semiconductor, and constituting the second lower electrode and the second capacitor; and A display device comprising a first active pattern disposed in the same layer as the first upper electrode and overlapping with the second lower electrode.
2. A display device according to claim 1, characterized in that the first lower electrode and the second upper electrode are electrically connected to each other.
3. A display device according to claim 1, characterized in that a high power supply voltage is provided to the first lower electrode and the second upper electrode.
4. A first lower electrode disposed on a base substrate; A first upper electrode disposed on the first lower electrode, overlapping with the first lower electrode, comprising a silicon semiconductor, and constituting the first lower electrode and the first capacitor; A second lower electrode disposed on the first upper electrode; and A second upper electrode disposed on the second lower electrode and overlapping with the second lower electrode, comprising an oxide semiconductor, and constituting the second lower electrode and the second capacitor, and A display device characterized in that the first upper electrode and the second lower electrode are electrically connected to each other.
5. A display device according to claim 1, characterized in that the first lower electrode and the second lower electrode comprise the same material.
6. A display device according to claim 5, wherein the first lower electrode and the second lower electrode comprise molybdenum.
7. delete
8. In Article 1, A display device characterized by further including a first lower gate electrode disposed in the same layer as the first lower electrode and overlapping with the second lower electrode.
9. A display device according to claim 8, characterized in that a gate signal is provided to the first lower gate electrode and the second lower electrode.
10. A first lower electrode disposed on a base substrate; A first upper electrode disposed on the first lower electrode, overlapping with the first lower electrode, comprising a silicon semiconductor, and constituting the first lower electrode and the first capacitor; A second lower electrode disposed on the first upper electrode; and A second upper electrode disposed on the second lower electrode and overlapping with the second lower electrode, comprising an oxide semiconductor, and constituting the second lower electrode and the second capacitor, and A second active pattern disposed on the same layer as the second upper electrode; and A display device characterized by further including an upper gate electrode disposed on the second active pattern and overlapping with the second active pattern.
11. A display device according to claim 10, wherein the first lower electrode and the first upper electrode overlap with the upper gate electrode.
12. A display device according to claim 10, characterized in that the first lower electrode and the first upper electrode do not overlap with the upper gate electrode.
13. In Article 12, A display device characterized by further including a second lower gate electrode disposed in the same layer as the second lower electrode and overlapping with the upper gate electrode.
14. A display device according to claim 13, characterized in that a gate signal is provided to the upper gate electrode and the second lower gate electrode.
15. A first lower electrode disposed on a base substrate; An upper electrode disposed on the first lower electrode, overlapping with the first lower electrode, comprising a silicon semiconductor, and constituting a capacitor with the first lower electrode; A first active pattern disposed on the same layer as the upper electrode; A second lower electrode disposed on the first active pattern and overlapping with the first active pattern; A second active pattern disposed on the second lower electrode and comprising an oxide semiconductor; and A display device comprising an upper gate electrode disposed on the second active pattern and overlapping with the second active pattern.
16. In Article 15, A display device characterized by further including a first lower gate electrode disposed in the same layer as the first lower electrode and overlapping with the second lower electrode.
17. A display device according to claim 16, characterized in that a gate signal is provided to the second lower electrode and the first lower gate electrode.
18. A display device according to claim 15, wherein the first lower electrode and the upper electrode overlap with the upper gate electrode.
19. A display device according to claim 15, characterized in that the first lower electrode and the upper electrode do not overlap with the upper gate electrode.
20. In Article 19, A display device characterized by further including a second lower gate electrode disposed in the same layer as the second lower electrode and overlapping with the upper gate electrode.

Description

Pixel circuit and display device including the same The present invention relates to a pixel circuit and a display device including the same. A display device includes a pixel structure, and the pixel structure includes a plurality of wires and electrodes. In order to drive the display device at a high frequency, the number of wires and electrodes included in the pixel structure is increasing. Furthermore, in order for an image with high resolution to be displayed on the display device, the area of the pixel structure needs to be reduced. Accordingly, a structure in which the wires and electrodes are stacked is being developed. At the same time, in order to increase the yield of the display device, efficiency in the process of forming the wires and electrodes is required. FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention. Figure 2 is a circuit diagram showing an example of a pixel circuit included in the display device of Figure 1. FIG. 3 is a cross-sectional view showing an example of a pixel structure included in the display device of FIG. 1. FIGS. 4 to 9 are cross-sectional views for explaining a method of manufacturing the pixel structure of FIG. 3. Figure 10 is a circuit diagram showing another example of a pixel circuit included in the display device of Figure 1. FIG. 11 is a cross-sectional view showing another example of a pixel structure included in the display device of FIG. 1. FIGS. 12 to 17 are cross-sectional views for explaining a method of manufacturing the pixel structure of FIG. 11. Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are given the same reference numerals, and redundant descriptions of identical components are omitted. FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention. Referring to FIG. 1, a display device (1000) according to one embodiment of the present invention may include a display panel (PNL), a data driving unit (DDV), a gate driving unit (GDV), and a control unit (CON). The above display panel (PNL) may include data lines (DL), gate lines (GL), and pixel structures (PX). The data lines (DL) may extend in a first direction (D1) and may be spaced apart from each other in a second direction (D2) that intersects the first direction (D1). The gate lines (GL) may extend in the second direction (D2) and may be spaced apart from each other in the first direction (D1). The pixel structures (PX) may be placed in the area where the data lines (DL) and the gate lines (GL) intersect. The pixel structures (PX) may be electrically connected to the data lines (DL) and the gate lines (GL). The pixel structures (PX) may be provided with a data voltage (DATA), a gate signal (GS), a high power voltage (ELVDD), and a low power voltage (ELVSS). The data driver (DDV) can generate the data voltage (DATA) based on the output image data (ODAT) and the data control signal (DCTRL). The data voltage (DATA) can be provided to the pixel structure (PX_1) through the data line (DL). For example, the data driver (DDV) can generate the data voltage (DATA) corresponding to the output image data (ODAT) and output the data voltage (DATA) in response to the data control signal (DCTRL). The data control signal (DCTRL) may include an output data enable signal, a horizontal start signal, and a load signal. In one embodiment, the data driver (DDV) may be electrically connected to the display panel (PNL) by one or more integrated circuits (IC). In another embodiment, the data driver (DDV) may be mounted on the display panel (PNL) or integrated into the periphery of the display panel (PNL). The gate driver (GDV) can generate the gate signal (GS) based on the gate control signal (GCTRL). The gate signal (GS) can be provided to the pixel structure (PX_1) through the gate line (GL). For example, the gate signal (GS) may include a gate-on voltage that turns on the transistor and a gate-off voltage that turns off the transistor. The gate driver (GDV) can sequentially provide the gate-on voltage to the pixel structures (PX_1) through the gate lines (GL). For example, the gate control signal (GCTRL) may include a vertical start signal, a clock signal, etc. In one embodiment, the gate driver (GDV) may be mounted on the display panel (PNL). In another embodiment, the gate driver (GDV) may be electrically connected to the display panel (PNL) in the form of the COF. The above control unit (CON) (e.g., timing controller (T-CON)) may receive input image data (IDAT) and control signals (CTRL) from an external host processor (e.g., GPU). For example, the input image data (IDAT) may be RGB data including red image data, green image data, and blue image data. The control signals (CTRL) may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock sig