KR-102960274-B1 - INTEGRATED CIRCUIT INCLUDING A MEMORY CELL AND METHOD OF DESIGNATING THE SAME

Abstract

An integrated circuit according to the technical concept of the present disclosure comprises: a first wiring layer in which a first bitline pattern and a positive power pattern providing a positive supply voltage are formed extending in a first direction, and a plurality of first power line landing pads providing a negative supply voltage and a plurality of first wordline landing pads providing a wordline voltage are formed; a first negative power pattern extending in a second direction perpendicular to the first direction and connecting first power line landing pads adjacent to the second direction among the first power line landing pads and providing a negative supply voltage; a second wiring layer in which a plurality of first wordline patterns providing a wordline voltage are formed extending in a second direction and connected to a plurality of first wordline landing pads; a third wiring layer in which a second negative power pattern connected to the first negative power pattern and a plurality of second wordline landing pads connected to a plurality of first wordline patterns are formed; and a fourth wiring layer in which a plurality of second wordline patterns providing a wordline voltage are formed extending in a second direction and connected to a plurality of second wordline landing pads.

Inventors

• 이인학
• 이승훈
• 백상엽
• 박승한
• 이혜진

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20210310

Priority Date

20200731

Claims (20)

1. As an integrated circuit including memory cells, A first wiring layer in which a first bitline pattern and a positive power pattern providing a positive supply voltage are extended in a first direction and a plurality of first power line landing pads providing a negative supply voltage and a plurality of first wordline landing pads providing a wordline voltage are formed; A first negative power pattern extending in a second direction perpendicular to the first direction and connecting the first power line landing pads adjacent to the second direction among the first power line landing pads and providing the negative supply voltage; and a second wiring layer having a plurality of first word line patterns formed therein, extending in the second direction and connected to the plurality of first word line landing pads and providing the word line voltage; A third wiring layer in which a second negative power pattern connected to the first negative power pattern and a plurality of second wordline landing pads connected to the plurality of first wordline patterns are formed; and It includes a fourth wiring layer in which a plurality of second wordline patterns are formed, which extend in the second direction, are connected to the plurality of second wordline landing pads, and provide the wordline voltage, and The above plurality of second wordline patterns are, An integrated circuit characterized by being arranged adjacent to each other in the above-mentioned fourth wiring layer.
2. In paragraph 1, The above second negative power pattern is, An integrated circuit characterized by being formed by extending in the first direction from the third wiring layer.
3. In paragraph 1, The above second negative power pattern is, An integrated circuit characterized by being formed as a mesh structure in the third wiring layer above.
4. In paragraph 1, An integrated circuit further comprising a first via layer in which a first via extending in a third direction perpendicular to the first direction and the second direction and connecting the adjacent first power line landing pads and the first negative power pattern, and a second via extending in the third direction and connecting the first word line landing pad and the first word line pattern are formed.
5. In paragraph 4, The cross-sectional area of the first via above is, An integrated circuit characterized by having a cross-sectional area larger than that of the second via.
6. In paragraph 4, An integrated circuit characterized in that the width of the first via is longer than the width of the second direction.
7. In paragraph 4, An integrated circuit further comprising a second via layer in which a third via extending in the third direction and connecting the first negative power pattern and the second negative power pattern, and a fourth via extending in the third direction and connecting the first wordline pattern and the second wordline landing pad are formed.
8. In Paragraph 7, The cross-sectional area of the third via above is, An integrated circuit characterized by having a cross-sectional area larger than that of the fourth via.
9. In paragraph 1, The width of the area adjacent to the first negative power pattern among the first wordline patterns is, An integrated circuit characterized by having a width shorter than that of the area not adjacent to the first negative power pattern among the first wordline patterns.
10. In paragraph 1, An integrated circuit characterized by further including a bitline landing pad formed in the second wiring layer and connected to the first bitline pattern.
11. delete
12. In an integrated circuit including a memory cell, A bitline structure including a first bitline pattern formed on a first wiring layer, providing a bitline voltage to the memory cell and extending in a first direction; A wordline structure comprising: a plurality of first wordline landing pads formed in the first wiring layer and providing a wordline voltage to the memory cell; a first wordline pattern formed in the second wiring layer, extending in a second direction perpendicular to the first direction and connected to the plurality of first wordline landing pads; a plurality of second wordline landing pads formed in the third wiring layer and connected to the first wordline pattern; and a plurality of second wordline patterns formed in the fourth wiring layer, extending in the second direction and connected to the plurality of second wordline landing pads; and A negative power line structure comprising a plurality of first power line landing pads formed in the first wiring layer and providing a negative supply voltage to the memory cell, a first negative power pattern formed in the second wiring layer and extending in the second direction and connecting second power line landing pads adjacent to the first power line landing pads in the second direction, and a second negative power pattern formed in the third wiring layer and connected to the first negative power pattern, At least a portion of the first wordline pattern above is, Adjacent to the above first negative power pattern, and The width of the area adjacent to the first negative power pattern among the first wordline patterns is, An integrated circuit characterized by being shorter than the width of the area not adjacent to the first negative power pattern among the first wordline patterns.
13. In Paragraph 12, The above second negative power pattern is, An integrated circuit characterized by being formed by extending in the first direction from the third wiring layer.
14. In Paragraph 12, The above second negative power pattern is, An integrated circuit characterized by being formed as a mesh structure in the third wiring layer above.
15. delete
16. A method for designing an integrated circuit including a memory cell, A step of creating a path that provides a wordline voltage to the memory cell; A step of creating a path that provides a negative supply voltage to the memory cell; and The method includes the step of creating a path that provides a bitline voltage to the memory cell; and The step of creating a path that provides a negative supply voltage to the memory cell is: A step of creating a plurality of first power line landing pads in a first wiring layer that provide the negative supply voltage to the memory cell; A step of generating a first negative power pattern that extends in a second direction to a second wiring layer and connects first power line landing pads adjacent in the second direction among the plurality of first power line landing pads; and The method includes the step of generating a second negative power pattern connected to the first negative power pattern in a third wiring layer, The step of creating a path that provides the above bitline voltage is, A method for designing an integrated circuit, characterized by including the step of forming a bitline landing pad on the second wiring layer so as to be connected to a first bitline pattern formed on the first wiring layer.
17. In Paragraph 16, The above second negative power pattern is, A method for designing an integrated circuit characterized by being in the form of a line extending in a first direction perpendicular to the second direction.
18. In Paragraph 16, The above second negative power pattern is, A method for designing an integrated circuit characterized by a mesh form in which wirings extending in the second direction and wirings extending in the first direction perpendicular to the second direction are connected.
19. In Paragraph 16, The step of creating a path that provides a wordline voltage to the memory cell is: A step of creating a plurality of first wordline landing pads on the first wiring layer; A step of generating a first wordline pattern that extends in the second direction to the second wiring layer and is connected to the plurality of first wordline landing pads; A step of creating a plurality of second wordline landing pads connected to the first wordline pattern on the third wiring layer; and A method for designing an integrated circuit, characterized by including the step of generating a plurality of second wordline patterns that extend in the second direction and are connected to the plurality of second wordline landing pads in the fourth wiring layer.
20. In Paragraph 19, The step of creating a path that provides a negative supply voltage to the memory cell is: The method further includes the step of creating a first via formed in a first via layer and connecting the adjacent first power line landing pads and the first negative power pattern, The step of creating a path that provides a wordline voltage to the memory cell is: The method further includes the step of creating a second via formed in the first via layer and connecting the first wordline landing pad and the first wordline pattern, The cross-sectional area of the first via above is, A method for designing an integrated circuit characterized by having a cross-sectional area larger than that of the second via.

Description

Integrated circuit including a memory cell and method of designing the same The technical concept of the present disclosure relates to an integrated circuit, and more specifically, to an integrated circuit including a memory cell. Due to the demand for high integration density and advancements in semiconductor processes, the width, spacing, and/or height of wiring included in integrated circuits may decrease, while parasitic elements and resistance of the wiring may increase. Consequently, the driving characteristics of the paths providing voltage to standard cells within the integrated circuit may degrade. Furthermore, to achieve reduced power consumption and higher operating speeds, the power supply voltage of the integrated circuit may be reduced; consequently, the impact of parasitic elements and resistance of the wiring on the integrated circuit may become more significant. Despite these parasitic elements and resistance, memory devices manufactured by semiconductor processes may be required to reliably provide high performance according to the requirements of various applications. FIG. 1 is a drawing for illustrating an integrated circuit including a mixed row block according to an exemplary embodiment of the present disclosure. FIG. 2 is a circuit diagram illustrating a memory cell according to an exemplary embodiment of the present disclosure. FIG. 3 is a cross-sectional view illustrating a wiring layer according to an exemplary embodiment of the present disclosure. FIG. 4 is a plan view showing the arrangement of a memory cell array according to an exemplary embodiment of the present disclosure. FIG. 5 is a plan view showing the layout of a memory cell array according to an exemplary embodiment of the present disclosure. FIGS. 6a and 6b are cross-sectional views showing examples of cell structures according to exemplary embodiments of the present disclosure. FIGS. 6c and 6d are cross-sectional views showing examples of cells of a Gate All Around (GAA) structure according to exemplary embodiments of the present disclosure. FIG. 7 is a plan view illustrating a wiring layer of a memory cell array according to an exemplary embodiment of the present disclosure. FIG. 8a is a plan view illustrating a wiring layer of a memory cell array according to an exemplary embodiment of the present disclosure. FIG. 8b is a plan view illustrating a wiring layer of a memory cell array according to an exemplary embodiment of the present disclosure. FIG. 9 is a plan view illustrating a wiring layer of a memory cell array according to an exemplary embodiment of the present disclosure. FIG. 10 is a plan view illustrating a wiring layer of a memory cell array according to an exemplary embodiment of the present disclosure. FIG. 11a is a plan view illustrating a wiring layer of a memory cell array according to an exemplary embodiment of the present disclosure. FIG. 11b is a plan view illustrating a wiring layer of a memory cell array according to an exemplary embodiment of the present disclosure. FIG. 12 is a plan view illustrating a wiring layer of a memory cell array according to an exemplary embodiment of the present disclosure. FIG. 13 is a plan view illustrating a wiring layer of a memory cell array according to an exemplary embodiment of the present disclosure. FIG. 14a is a plan view showing a wiring layer of a memory cell array according to an exemplary embodiment of the present disclosure. FIG. 14b is a plan view showing a wiring layer of a memory cell array according to an exemplary embodiment of the present disclosure. FIG. 15 is a plan view showing a wiring layer of a memory cell array according to an exemplary embodiment of the present disclosure. FIG. 16 is a flowchart illustrating a method for manufacturing an integrated circuit according to an exemplary embodiment of the present disclosure. FIG. 17 is a flowchart illustrating an example of step S400 of FIG. 13 according to an exemplary embodiment of the present disclosure. FIG. 18 is a flowchart illustrating an example of step S440 of FIG. 14 according to an exemplary embodiment of the present disclosure. FIG. 19 is a block diagram showing a system-on-chip (SoC) (200) according to an exemplary embodiment of the present disclosure. FIG. 20 is a block diagram showing a computing system (300) including a memory for storing a program according to an exemplary embodiment of the present disclosure. Hereinafter, various embodiments of the present invention are described with reference to the accompanying drawings. FIG. 1 is a drawing for illustrating a memory device according to an exemplary embodiment of the present disclosure. Referring to FIG. 1, the memory device (100) may include a precharge circuit (110), a row decoder (120), a cell array (130), a column decoder (140), a data buffer (150), and a sensing amplifier (160). Although not shown in FIG. 1, in some embodiments, the memory device (100) may further include an address decoder, a read circuit, a data input