KR-102960280-B1 - Method of programming non-volatile memory device

KR102960280B1KR 102960280 B1KR102960280 B1KR 102960280B1KR-102960280-B1

Abstract

A method for programming a non-volatile memory device comprises the steps of: applying a first voltage to a first word line group and a selected word line that are relatively close to a selected word line and where a program operation is performed, in a first channel initialization section, and applying a second voltage lower than the first voltage to a second word line group that is relatively far from the selected word line and where a program operation is performed; applying a first program voltage to a selected word line in a first program execution section for performing a first program for data; applying a first voltage to a selected word line and a first word line group and applying a second voltage to a second word line group in a second channel initialization section; and applying a second program voltage to a selected word line in a second program execution section for performing a second program for data.

Inventors

조성민

Assignees

삼성전자주식회사

Dates

Publication Date: 20260507
Application Date: 20220114
Priority Date: 20211110

Claims (20)

As a method for programming a non-volatile memory device, In a first channel initialization section, a first voltage is applied to a first word line group that is relatively close to a selected word line and where a program operation is performed, and to the selected word line; and a second voltage lower than the first voltage is applied to a second word line group that is relatively far from the selected word line and where a program operation is performed; A step of applying a first program voltage to the selected word line in a first program execution section for executing a first program for data; In the second channel initialization section, the step of applying the first voltage to the selected word line and the first word line group, and applying the second voltage to the second word line group; A step of applying a second program voltage to the selected word line in a second program execution section for executing a second program for the above data; Between the first program execution section and the second channel initialization section, a step of performing a first program for adjacent word lines included in a third word line group; and In the second channel initialization section, the method includes the step of applying the first voltage to the adjacent word line, A method characterized in that the second channel initialization section is after the first program for the adjacent word line.
In paragraph 1, The above-mentioned selection word line is disposed between the third word line group and the first word line group disposed on the upper part of the substrate, and The first word line group is positioned above the selected word line, and A method characterized in that the second word line group is positioned above the first word line group.
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In paragraph 2, In the first channel initialization section, a step of applying a ground voltage to the third word line group; and A method further comprising the step of applying the ground voltage to at least one word line other than the adjacent word line in the third word line group during the second channel initialization section.
In paragraph 2, A method further comprising the step of applying a third voltage lower than the second voltage to the first and second word line groups and the selected word line in the word line setup section between the second channel initialization section and the second program execution section, and applying a fourth voltage lower than the first voltage to the adjacent word line.
In paragraph 5, A method characterized in that, in the word line setup section above, the program operation for memory cells connected to the first and second word line groups is in a completed state, and the program operation for memory cells connected to the adjacent word line is in an incomplete state.
In paragraph 1, A method characterized by further including the step of applying a third voltage lower than the first and second voltages to the first and second word line groups and the selected word line in the word line setup section between the first channel initialization section and the first program execution section.
In Paragraph 7, A method characterized in that the above third voltage corresponds to the ground voltage.
In paragraph 1, A program operation to write the data to a memory cell connected to the selected word line through the first and second programs is completed, and By the first program above, the memory cell is programmed from an erased state to one of N program states, and The above second program corresponds to reprogramming the memory cell, and A method characterized in that N is a positive integer.
In paragraph 1, A program operation to write the data to a memory cell connected to the selected word line through the first and second programs is completed, and By the first program above, the memory cell is programmed from an erased state to one of M program states, and By the second program above, the memory cell is programmed from one of the M program states to one of the N program states, and A method characterized in that M and N are positive integers, and N is greater than M.
In paragraph 1, The non-volatile memory device comprises a second word line group disposed on the upper part of a substrate, a first word line group disposed on the upper part of the second word line group, a selected word line disposed on the upper part of the first word line group, and a third word line group disposed on the upper part of the selected word line. The above method further comprises the step of performing a first program for an adjacent word line included in the third word line group between the first program execution section and the second channel initialization section.
In paragraph 1, A method characterized in that, in the first and second channel initialization intervals, a precharge voltage is applied to a common source line, a bit line program voltage is applied to a selected bit line, and a bit line program prohibition voltage is applied to a non-selected bit line.
In paragraph 1, The above non-volatile memory device comprises a plurality of memory stacks, including a first memory stack extended vertically on a substrate and a second memory stack extended vertically above the first memory stack. When the above-mentioned selected word line and the above-mentioned first and second word line groups are connected to the first memory stack, in the above-mentioned first and second channel initialization intervals, the same voltage is applied to the word lines connected to the second memory stack, and A method characterized in that, when the selected word line and the first and second word line groups are connected to the second memory stack, the same voltage is applied to the word lines connected to the first memory stack during the first and second channel initialization intervals.
As a method for programming a non-volatile memory device, A step of performing a first program operation for first memory cells connected to a first selection word line by applying a first program voltage to a first selection word line in a first program execution section for performing a first program for first data; A step of performing a first program operation for second memory cells connected to a second selection word line adjacent to the first selection word line; In a word line setup section after the step of performing the first program operation for the second memory cells, a step of applying a first bias voltage to the first selected word line and applying a second bias voltage having a voltage level higher than the first bias voltage to the second selected word line; and A method comprising the step of performing a second program operation for the first memory cells by applying a second program voltage to the first selected word line in a second program execution section for performing a second program for the first data.
In Paragraph 14, The above first bias voltage corresponds to the ground voltage, and A method characterized in that the second bias voltage corresponds to a voltage level that turns on the second memory cells.
In Paragraph 14, A method further comprising the step of applying the first bias voltage to the first and second selected word lines in the word line setup section prior to the first program execution section.
In Paragraph 14, A program operation for writing the first data to the first memory cells is completed through the first and second program operations above, and By the above first program operation, the first memory cells are each programmed from an erased state to one of N program states, and The above second program operation corresponds to a reprogram operation for the first memory cells, and A method characterized in that N is a positive integer.
In Paragraph 14, A program operation for writing the first data to the first memory cells is completed through the first and second program operations above, and By the above first program operation, the first memory cells are each programmed from an erased state to one of M program states, and By the above second program operation, the first memory cells are each programmed from one of the M program states to one of the N program states, and A method characterized in that M and N are positive integers, and N is greater than M.
As a method for programming a non-volatile memory device, A step of applying a precharge voltage to the common source line during the channel initialization period; In a bit line setup section, a program operation is performed and a first word line positioned above a selected word line and a first voltage is applied to the selected word line, and the program operation is completed and a second voltage lower than the first voltage is applied to a second word line positioned above the first word line; In the word line setup section, a step of applying a third voltage lower than the first and second voltages to the selected word line and the first and second word lines; and In the program execution section, the step of executing program operations for memory cells connected to the selected word line is included, and A method characterized in that the above channel initialization section and the above bit line setup section correspond substantially to the same time section.
In Paragraph 19, A method characterized in that the above third voltage corresponds to the ground voltage.

Description

Method of programming non-volatile memory device The technical concept of the present disclosure relates to a memory device, and more specifically, to a method of programming a non-volatile memory device comprising first and second programs that are executed sequentially. Memory devices are used to store data and are classified into volatile memory devices and non-volatile memory devices. In response to the demand for increased capacity and miniaturization of non-volatile memory devices, a three-dimensional memory device comprising multiple cell strings extending vertically on a substrate has been developed. During the channel initialization phase for executing a program, channel initialization or precharge operations may be performed for the multiple cell strings. At this time, if the memory cells located at the top of the cell string are in a programmed state, a portion of the channel corresponding to the programmed memory cells may be negatively boosted, and due to the high threshold voltage of the programmed memory cells, the channel initialization or precharge operations may not be properly performed. Consequently, problems such as program disturbance or hot carrier injection (HCI) may occur, which may degrade the reliability of the non-volatile memory device. U.S. Patent Application Publication US 2021/0020256 (published Jan. 21, 2021) discloses a nonvolatile memory device and a method for programming the same, which performs programming considering the geometry of a cell string. Published Patent Application No. 10-2020-0052664 (published May 15, 2020) discloses a method for programming a nonvolatile memory device that can reduce disturbances received by memory cells during a programming operation. FIG. 1 is a block diagram showing a memory system according to one embodiment of the present disclosure. FIG. 2 is a block diagram showing a memory device according to one embodiment of the present disclosure. FIG. 3 is a circuit diagram showing a memory block according to one embodiment of the present disclosure. FIGS. 4a and 4b are perspective views showing memory blocks according to some embodiments of the present disclosure, respectively. FIG. 5 schematically illustrates a memory cell array according to one embodiment of the present disclosure. FIG. 6 illustrates a program operation including a first program operation and a second program operation for a selected word line according to one embodiment of the present disclosure. FIG. 7 illustrates first and second program operations according to one embodiment of the present disclosure. FIG. 8 illustrates first and second program operations according to one embodiment of the present disclosure. FIG. 9 is a flowchart illustrating a method for programming a memory device according to one embodiment of the present disclosure. FIG. 10 is a timing diagram showing the program operation of a memory device according to one embodiment of the present disclosure. FIG. 11 schematically illustrates a memory cell array according to one embodiment of the present disclosure. FIGS. 12a and FIGS. 12b illustrate an exemplary program sequence according to some embodiments of the present disclosure. FIG. 13 illustrates a program operation including first and second program operations for a selected word line and a program operation including first and second program operations for an adjacent word line, according to one embodiment of the present disclosure. FIG. 14 is a flowchart illustrating a programming method of a memory device according to one embodiment of the present disclosure. FIG. 15 is a timing diagram showing a first program operation of a memory device according to one embodiment of the present disclosure. FIG. 16 is a timing diagram showing a second program operation of a memory device according to one embodiment of the present disclosure. FIG. 17 is a flowchart illustrating a method for programming a memory device according to one embodiment of the present disclosure. FIG. 18 is a flowchart illustrating a programming method of a memory device according to one embodiment of the present disclosure. FIG. 19a is a timing diagram showing a second program operation for a first selected word line according to a comparative example of the present disclosure, and FIG. 19b is a timing diagram showing a second program operation for a first selected word line according to an embodiment of the present disclosure. FIG. 20 is a flowchart illustrating a method for programming a memory device according to one embodiment of the present disclosure. FIG. 21 is a flowchart illustrating a method for programming a memory device according to one embodiment of the present disclosure. FIG. 22 is a timing diagram showing the program operation of a memory device according to one embodiment of the present disclosure. FIG. 23 shows a memory device having a COP structure according to one embodiment of the present disclosure. FIG. 24 is a cross-sectional view showing a memory device having a