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KR-102960620-B1 - DISPLAY DEVICE AND TILE SHAPED DISPLAY DEVICE

KR102960620B1KR 102960620 B1KR102960620 B1KR 102960620B1KR-102960620-B1

Abstract

A display device and a tile-type display device including the same are provided. The display device includes a transistor array layer disposed on a first surface of a substrate, and a plurality of light-emitting elements disposed in a display area on the transistor array layer. The transistor array layer includes a plurality of pixel drivers disposed in a circuit area that is part of the display area, two or more gate drivers, a first gate voltage supply line disposed around the circuit area in the display area, and two or more first gate voltage auxiliary lines connected between each of the two or more gate drivers and the first gate voltage supply line. And, one end of each of the two or more first gate voltage auxiliary lines is spaced further apart from the edge of the substrate adjacent to the first gate voltage supply line than the first gate voltage supply line.

Inventors

  • 최병균
  • 김병용
  • 이재필

Assignees

  • 삼성디스플레이 주식회사

Dates

Publication Date
20260507
Application Date
20220426
Priority Date
20220127

Claims (20)

  1. A substrate comprising a display area in which a plurality of subpixels are arranged and a non-display area surrounding the display area; A transistor array layer disposed on a first surface of the above substrate; and It includes a plurality of light-emitting elements disposed in the display area on the transistor array layer and corresponding to each of the plurality of subpixels, Some of the above-mentioned display areas are circuit areas, and The above transistor array layer A plurality of pixel driving units disposed in the circuit area and electrically connected to each of the plurality of light-emitting elements; Gate wirings disposed in the circuit area and extending in one direction, transmitting gate signals to the plurality of pixel drivers; Two or more gate drivers disposed in the circuit area and spaced apart from each other in the one direction, supplying the gate signals to the gate wires; A first gate voltage supply wiring disposed around the circuit area among the above display areas and extending in the one direction; and It includes two or more first gate voltage auxiliary wires that extend in another direction intersecting the first direction from the first gate voltage supply wire and are electrically connected between the two or more gate drivers and the first gate voltage supply wire, Each of the above plurality of pixel driving units includes at least one transistor, and The first gate voltage supply wiring and the two or more first gate voltage auxiliary wirings transmit a first gate level voltage for generating the gate signals to the two or more gate drivers, and Each of the above two or more first gate voltage auxiliary wires is electrically connected to the first gate voltage supply wire through at least one first gate voltage wire contact hole, and A display device in which one end of each of the two or more first gate voltage auxiliary lines is spaced further from the edge of the substrate adjacent to the first gate voltage supply line in the other direction than the first gate voltage supply line.
  2. In Article 1, A display device in which each of the above plurality of light-emitting elements is a flip-chip type micro light-emitting diode element.
  3. In Article 1, A plurality of pixels are provided, each comprising two or more subpixels adjacent to one direction or the other direction among the plurality of subpixels. It further includes an anti-static pattern disposed on a part of the non-display area of the first surface of the substrate, and The above anti-static pattern includes a main pattern arranged parallel to the edge of the display area and a plurality of sub-patterns protruding from the main pattern toward the display area. The above plurality of sub-patterns are each disposed between the pixels adjacent to the main pattern among the plurality of pixels, and At least one of the plurality of sub-patterns is a display device that overlaps with the first gate voltage wiring contact hole.
  4. In Paragraph 3, The first gate voltage supply wiring is a display device positioned adjacent to the main pattern of the electrostatic discharge prevention pattern.
  5. In Paragraph 3, The above non-display area includes at least one pad area in which pads connected to the transistor array layer are arranged, and The above anti-static pattern is a display device spaced apart from the pad area.
  6. In Article 5, Connection wiring disposed on a second surface of the substrate opposite to a first surface of the substrate; and It further includes side wirings disposed on one side between the first surface and the second surface of the substrate and respectively connected between the pads and the connecting wirings, The above connecting wiring is a display device connected to a flexible film through a conductive adhesive member.
  7. In Paragraph 3, A display device in which one end of each of the two or more first gate voltage auxiliary wires extends in the one direction and overlaps with the first gate voltage supply wire.
  8. In Paragraph 3, The above transistor array layer A second gate voltage supply wiring disposed around the circuit area among the above display areas, extending in the one direction and spaced further from the edge of the substrate than the first gate voltage supply wiring; and It further includes two or more second gate voltage auxiliary wires that extend in the other direction and are connected between each of the two or more gate driving units and the second gate voltage supply wire, The second gate voltage supply wiring and the two or more second gate voltage auxiliary wirings transmit a second gate level voltage for generating the gate signals to the two or more gate drivers, and A display device having a voltage level different from the first gate level voltage, wherein the second gate level voltage is the same as the first gate level voltage.
  9. In Paragraph 3, The above transistor array layer A gate insulating film covering a semiconductor layer on the first surface of the substrate; A first interlayer insulating film covering a first conductive layer on the gate insulating film; A second interlayer insulating film covering a second conductive layer on the first interlayer insulating film; A first planarization film covering a third conductive layer on the second interlayer insulating film; A second planarization film covering a fourth conductive layer on the first planarization film; and It includes a third planarization film covering a fifth conductive layer on the second planarization film, and The above first gate voltage supply wiring is composed of the above third conductive layer, and A display device comprising the above two or more first gate voltage auxiliary wirings and the above fourth conductive layer.
  10. In Article 9, The above transistor array layer A plurality of anode electrodes each corresponding to the plurality of subpixels and comprising a sixth conductive layer on the third planarization film; A plurality of cathode electrodes each corresponding to the plurality of subpixels and adjacent to the plurality of anode electrodes, and each comprising the sixth conductive layer; A plurality of anode pads each covering the plurality of anode electrodes and a seventh conductive layer on the sixth conductive layer; and It further includes a plurality of cathode pads formed of the seventh conductive layer, each covering the plurality of cathode electrodes. The above seventh conductive layer is made of a transparent conductive material, and The above plurality of light-emitting elements are each disposed on the above plurality of anode pads and the above plurality of cathode pads in a display device.
  11. In Article 10, The above anti-static pattern is composed of the above seventh conductive layer, and A portion of the edge of the second planarization film adjacent to the edge of the substrate is exposed outside the third planarization film, and a portion of the edge of the first planarization film adjacent to the edge of the substrate is exposed outside the second planarization film, The plurality of sub-patterns of the above anti-static pattern are a display device in contact with the first planarization film, the second planarization film, and the third planarization film.
  12. In Article 10, The above transistor array layer Scan writing wiring to which a scan writing signal is applied from any one of the two or more gate driving units above; Scan initialization wiring to which a scan initialization signal is applied from any one of the two or more gate driving units above; Sweep signal wiring to which a sweep signal is applied from any one of the two or more gate drivers above; A first data wiring to which a first data voltage is applied; and It further includes a second data wiring to which a second data voltage is applied, and Each of the plurality of pixel driving units is connected to the scan writing wiring, the scan initialization wiring, the sweep signal wiring, the first data wiring, and the second data wiring, and One of the plurality of pixel driving units above is a pixel driving unit A first pixel driving circuit that generates a control current according to the first data voltage of the first data wiring; A second pixel driving circuit that generates a driving current applied to the anode electrode of one of the plurality of light-emitting elements according to the second data voltage of the second data wiring; and It includes a third pixel driving circuit that controls the period for applying the driving current to the anode electrode of the one light-emitting element according to the control current of the first pixel driving circuit, The above-mentioned first pixel driving circuit is, A first transistor that generates the control current according to the first data voltage; A second transistor that applies the first data voltage of the first data wiring to the first electrode of the first transistor according to the scan write signal; A third transistor that applies an initial voltage of an initial voltage wiring to the gate electrode of the first transistor according to the scan initialization signal; A fourth transistor connecting the gate electrode and the second electrode of the first transistor according to the above scan write signal; and A display device comprising a first capacitor disposed between the sweep signal wiring and the gate electrode of the first transistor.
  13. In Article 12, The above transistor array layer A first power wiring to which a first power voltage is applied; Second power wiring to which a second power voltage is applied; A first light-emitting wiring to which a first light-emitting signal is applied from any one of the two or more gate drivers; and It further includes a scan control wiring to which a scan control signal is applied from any one of the two or more gate driving units above, and The above two or more first gate voltage auxiliary wirings are further connected to the pixel driving unit of each of the plurality of subpixels, and The above-mentioned first pixel driving circuit is, A fifth transistor that connects the first power wiring to the first electrode of the first transistor according to the first light emission signal; A sixth transistor that connects the second electrode of the first transistor to the third pixel driving circuit according to the first light emission signal; and A display device further comprising a seventh transistor that connects a first node between the sweep signal wiring and the first capacitor to the first gate voltage auxiliary wiring according to the scan control signal.
  14. In Article 13, The above second pixel driving circuit An eighth transistor that generates the driving current according to the second data voltage; A ninth transistor that applies the second data voltage of the second data wiring to the first electrode of the eighth transistor according to the scan write signal; A 10th transistor that applies the initialization voltage of the initialization voltage wiring to the gate electrode of the 8th transistor according to the scan initialization signal; and A display device comprising an eleventh transistor that connects the gate electrode of the eighth transistor and the second electrode according to the above scan writing signal.
  15. In Article 14, The above second pixel driving circuit is, A 12th transistor that connects the 2nd power wiring to the 1st electrode of the 8th transistor according to the 1st light emission signal; A 13th transistor that connects the 1st power wiring to the 2nd node according to the above scan control signal; A 14th transistor that connects the second power wiring to the second node according to the first light emission signal; and A display device further comprising a second capacitor disposed between the gate electrode of the eighth transistor and the second node.
  16. In Article 15, The above third pixel driving circuit is connected to the sixth transistor of the above first pixel driving circuit at the third node, and The above third pixel driving circuit A 15th transistor including a gate electrode connected to the third node; A 16th transistor that connects the 3rd node to the initialization voltage wiring according to the scan control signal; A 17th transistor that connects the second electrode of the 15th transistor to the anode electrode according to a second light emission signal; A 18th transistor that connects the anode electrode to the initialization voltage wiring according to the scan control signal; and A display device comprising a third capacitor disposed between the third node and the initialization voltage wiring.
  17. In Article 16, The above transistor array layer A third power wiring connected to the plurality of cathode electrodes and to which a third power voltage is applied; A plurality of first anode connection electrodes corresponding to each of the plurality of subpixels; and It further includes a plurality of second anode connection electrodes, each corresponding to the plurality of subpixels and each connected to the plurality of first anode connection electrodes, The channel, source electrode, and drain electrode of each of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelveth, thirteenth, eleventh, fifteenth, sixteenth, seventeenth, and eleventh transistors are formed of the semiconductor layer, and The gate electrodes of each of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, eleventh, thirteenth, eleventh, thirteenth, and eleventh transistors, and the first, third, and fifth capacitor electrodes, which are one end of each of the first, second, and third capacitors, are formed of the first conductive layer. The second, fourth, and sixth capacitor electrodes, which are the other ends of each of the first, second, and third capacitors, are formed of the second conductive layer, and The initialization voltage wiring, the scan initialization wiring, the scan write wiring, the first light-emitting wiring, the second light-emitting wiring, the first power horizontal wiring to which the first power supply voltage is applied, the sweep signal wiring, the first gate voltage auxiliary wiring, the scan control wiring, and the third power auxiliary wiring to which the third power supply voltage is applied are formed by the third conductive layer. The first data wiring, the first power vertical wiring to which the first power voltage is applied, the second data wiring, and the plurality of first anode connection electrodes are formed of the fourth conductive layer, and The above second power wiring and the plurality of second anode connection electrodes are formed of the fifth conductive layer, A display device in which the third power wiring is spaced apart from the second power wiring and consists of the fifth conductive layer or the sixth conductive layer.
  18. It includes a plurality of display devices arranged side by side with each other, and a joint disposed between the plurality of display devices. One of the above plurality of display devices is A substrate comprising a display area in which a plurality of subpixels are arranged and a non-display area surrounding the display area; A transistor array layer disposed on a first surface of the above substrate; and It includes a plurality of light-emitting elements disposed in the display area on the transistor array layer and corresponding to each of the plurality of subpixels, Some of the above-mentioned display areas are circuit areas, and The above transistor array layer A plurality of pixel driving units disposed in the circuit area and electrically connected to each of the plurality of light-emitting elements; Gate wirings disposed in the circuit area and extending in one direction, transmitting gate signals to the plurality of pixel drivers; Two or more gate drivers disposed in the circuit area and spaced apart from each other in the one direction, supplying the gate signals to the gate wires; A first gate voltage supply wiring disposed around the circuit area among the above display areas and extending in the one direction; and It includes two or more first gate voltage auxiliary wires that extend in another direction intersecting the first direction from the first gate voltage supply wire and are electrically connected between the two or more gate drivers and the first gate voltage supply wire, Each of the above plurality of pixel driving units includes at least one transistor, and The first gate voltage supply wiring and the two or more first gate voltage auxiliary wirings transmit a first gate level voltage for generating the gate signals to the two or more gate drivers, and Each of the above two or more first gate voltage auxiliary wires is electrically connected to the first gate voltage supply wire through at least one first gate voltage wire contact hole, and A tile-type display device in which one end of each of the two or more first gate voltage auxiliary lines is spaced further from the edge of the substrate adjacent to the first gate voltage supply line in the other direction than the first gate voltage supply line.
  19. In Article 18, Each of the above plurality of light-emitting elements is a flip-chip type micro light-emitting diode element, forming a tile-type display device.
  20. In Article 18, In any one of the plurality of display devices, a plurality of pixels are provided, each comprising two or more subpixels adjacent to one direction or the other direction among the plurality of subpixels. One of the above plurality of display devices is It further includes an anti-static pattern disposed on a part of the non-display area of the first surface of the substrate, and The above anti-static pattern includes a main pattern arranged parallel to the edge of the display area and a plurality of sub-patterns protruding from the main pattern toward the display area. The above plurality of sub-patterns are each disposed between the pixels adjacent to the main pattern among the plurality of pixels, and A tile-type display device in which at least one of the plurality of sub-patterns overlaps with the first gate voltage wiring contact hole.

Description

Display device and tile-shaped display device including the same The present invention relates to a display device and a tile-type display device including the same. As the information society develops, the demand for display devices to display images is increasing in various forms. Display devices may be flat panel display devices such as Liquid Crystal Displays, Field Emission Displays, and Light Emitting Displays. A light-emitting display device may include an organic light-emitting display device comprising an organic light-emitting diode element as a light-emitting element, or a light-emitting diode display device comprising an inorganic light-emitting diode element such as an LED (Light Emitting Diode) as a light-emitting element. In the case of an organic light-emitting display device, the brightness or gradation of the light from the organic light-emitting diode element is adjusted by adjusting the magnitude of the driving current applied to the organic light-emitting diode element. However, since the wavelength of the light emitted by the inorganic light-emitting diode element varies depending on the driving current, the image quality may be lowered if driven in the same way as the organic light-emitting diode element. FIG. 1 is a perspective view showing a tile-type display device according to one embodiment. Figure 2 is an enlarged layout diagram showing area A of Figure 1 in detail. FIG. 3 is a cross-sectional view showing an example of a plane cut along B-B' of FIG. 2. Figure 4 is an enlarged layout diagram showing area B of Figure 1 in detail. FIG. 5 is a cross-sectional view showing an example of a plane cut along C-C' of FIG. 4. FIG. 6 is a block diagram showing a tile-type display device according to one embodiment. FIG. 7 is a plan view showing a display panel of a display device according to one embodiment. Figures 8 and 9 are drawings showing examples of pixels of Figure 7. FIG. 10 is a cross-sectional view showing an example of a plane cut along E-E' of FIG. 8. FIG. 11 is a block diagram showing any one of the display devices of FIG. 1. FIG. 12 is a circuit diagram showing an example of a pixel driving unit for any one of the multiple subpixels of FIG. 11. FIG. 13 is a layout diagram showing a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer of a first subpixel according to one embodiment. Figure 14 is an enlarged layout diagram showing the area I of Figure 13 in detail. Figure 15 is an enlarged layout diagram showing the area II of Figure 13 in detail. Figure 16 is an enlarged layout diagram showing the III region of Figure 13 in detail. FIG. 17 is a layout diagram showing an example of the fifth, sixth, and seventh conductive layers of the first subpixel illustrated in FIG. 13. FIG. 18 is a cross-sectional view showing an example of a plane cut along F-F' of FIG. 13 and FIG. 14. FIG. 19 is a cross-sectional view showing an example of a plane cut along G-G' of FIG. 13 and FIG. 14. FIG. 20 is a cross-sectional view showing an example of a plane cut along H-H' of FIG. 13 and FIG. 14. FIG. 21 is a cross-sectional view showing an example of a plane cut along I-I' of FIG. 13 and FIG. 14. FIG. 22 is a cross-sectional view showing an example of a plane cut along J-J' of FIG. 13 and FIG. 14. FIG. 23 is a cross-sectional view showing an example of a plane cut along K-K' of FIG. 13 and FIG. 14. FIG. 24 is a cross-sectional view showing an example of a plane cut along L-L' of FIG. 13, FIG. 14, FIG. 15 and FIG. 16. FIG. 25 is a cross-sectional view showing an example of a plane cut along M-M' of FIG. 13, FIG. 14 and FIG. 15. FIG. 26 is a cross-sectional view showing an example of a plane cut along N-N' of FIG. 13 and FIG. 16. FIG. 27 is a cross-sectional view showing an example of a plane cut along O-O' of FIG. 13, FIG. 16 and FIG. 17. FIG. 28 is a layout diagram showing a display panel of a display device according to one embodiment. FIG. 29 is a layout diagram showing an example of the P area of FIG. 28. FIG. 30 is a layout diagram showing an example of a third conductive layer and a fourth conductive layer placed in the Q region of FIG. 29. FIG. 31 is a layout diagram showing an example of a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer placed in the Q region of FIG. 29. FIG. 32 is a layout diagram showing an example of a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a seventh conductive layer placed in the Q region of FIG. 29. Figure 33 is a cross-sectional view showing a comparative example of a short circuit defect. FIG. 34 is a cross-sectional view showing an example of a plane cut along R-R' of FIG. 32. FIG. 35 is a cross-sectional view showing an example of a plane cut along S-S' of FIG. 32. FIG. 36 is a cross-sectional view showing another example of FIG. 34. The advantages and features of