KR-102960698-B1 - MEMORY DEVICE AND METHOD FOR THE SAME

KR102960698B1KR 102960698 B1KR102960698 B1KR 102960698B1KR-102960698-B1

Abstract

One embodiment relates to a memory device and may include: an electrode structure comprising a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked on a substrate; a trench formed in the electrode structure having an upper sidewall, a lower sidewall, a horizontal portion connecting the upper sidewall and the lower sidewall and parallel to the upper surface of the substrate; an insulating film filling the trench; and a slimming hole formed in one region of the electrode structure and the insulating film including the sidewall of the trench, the bottom surface of which is disposed on the electrode layer where the horizontal portion is located.

Inventors

오성래
성상현
신현수

Assignees

에스케이하이닉스 주식회사

Dates

Publication Date: 20260507
Application Date: 20220127

Claims (17)

An electrode structure comprising a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked on a substrate; A trench formed in the electrode structure and having an upper sidewall, a lower sidewall, a horizontal portion connecting the upper sidewall and the lower sidewall and parallel to the upper surface of the substrate; An insulating film filling the above trench; and A slimming hole formed in one region of the electrode structure including the side wall of the trench and the insulating film, with a bottom surface disposed in the electrode layer where the horizontal portion is located; A memory device characterized by including
In paragraph 1, It further includes a plurality of slits that penetrate the cell region of the electrode structure and extend in a first direction parallel to the upper surface of the substrate, and A memory device characterized in that the above trench is disposed in a slimming region of the electrode structure adjacent to the cell region of the electrode structure in the above first direction.
In paragraph 2, A memory device characterized in that the above trench is arranged in alignment with one of the plurality of slits and configured to divide the electrode structure.
In paragraph 2, A memory device characterized in that the above-described slimming hole is configured to penetrate one of the two side walls of the trench facing in a second direction that intersects the first direction and is parallel to the upper surface of the substrate.
In paragraph 2, A memory device characterized in that the above-mentioned slimming hole is configured to penetrate both side walls of the trench facing in a second direction that intersects the first direction and is parallel to the upper surface of the substrate.
In paragraph 1, It further includes a plurality of slits that penetrate the cell region and slimming region of the electrode structure and extend in a first direction parallel to the upper surface of the substrate to divide the electrode structure, A memory device characterized in that the trench and the slimming hole are configured between two adjacent slits in the slimming area.
A step of forming a multilayer stack by alternately stacking a plurality of first material layers and a plurality of second material layers on a substrate; A step of forming an upper sidewall, a lower sidewall, and a trench in the above multilayer stack that connects the upper sidewall and the lower sidewall and has a horizontal portion parallel to the upper surface of the substrate; A step of filling the above trench with an insulating film; A step of forming a mask pattern having an opening that exposes a region including the sidewall of the trench on the multilayer stack and the insulating film; A step of forming a slimming hole by etching the multilayer stack and the insulating film using the above mask pattern as an etching mask; Step of detecting the above horizontal portion; A method for manufacturing a memory device including
In Paragraph 7, A method for manufacturing a memory device, characterized in that the step of detecting the horizontal portion involves checking the point in time when the position of the side wall of the trench detected on the bottom surface of the slimming hole changes discontinuously by the distance between the upper side wall and the lower side wall.
In Paragraph 7, A method for manufacturing a memory device characterized by the step of detecting the horizontal portion by checking the point in time when the lower side wall begins to be detected on the bottom surface of the slimming hole.
An electrode structure comprising a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked on a substrate; A trench formed in the above electrode structure and having inclined sidewalls; A slimming hole formed in one region of the electrode structure including the side wall of the trench; and A memory device characterized by including a recess formed in the trench sidewall at the lower part of the slimming hole.
In Paragraph 10, It further includes a plurality of slits that penetrate the cell region of the electrode structure and extend in a first direction parallel to the upper surface of the substrate, and A memory device characterized in that the above trench is formed in the slimming region of the electrode structure adjacent to the cell region of the electrode structure in the above first direction.
In Paragraph 11, A memory device characterized in that the above trench is arranged in alignment with one of the plurality of slits and configured to divide the electrode structure.
In Paragraph 11, A memory device characterized in that the above-described slimming hole is configured to penetrate one of the two side walls of the trench facing in a second direction that intersects the first direction and is parallel to the upper surface of the substrate.
In Paragraph 11, A memory device characterized in that the above-mentioned slimming hole is configured to penetrate both side walls of the trench facing in a second direction that intersects the first direction and is parallel to the upper surface of the substrate.
In Paragraph 10, It further includes a plurality of slits that penetrate the cell region and slimming region of the electrode structure and extend in a first direction parallel to the upper surface of the substrate to divide the electrode structure, A memory device characterized in that the trench and the slimming hole are positioned between two adjacent slits in the slimming area.
A step of forming a multilayer stack by alternately stacking a plurality of first material layers and a plurality of second material layers on a substrate; A step of forming a trench having inclined sidewalls in the above multilayer stack; A step of forming a mask pattern having an opening that exposes a region including the sidewall of the trench on the multilayer stack; A step of etching the multilayer stack using the above mask pattern as an etching mask to form a slimming hole, and forming a recess on the side wall of the trench below the slimming hole; and A step of calculating the depth of the slimming hole based on the gap between the side wall of the trench and the side wall of the recess; A method for manufacturing a memory device including
In Paragraph 16, The depth of the above slimming hole is, A method for manufacturing a memory device characterized by obtaining a proportional relationship between the gap between the sidewall of the trench and the sidewall of the recess and the depth of the slimming hole through several experiments, and calculating using the obtained relationship.

Description

Memory Device and Method for Manufacturing the Same The present invention relates to semiconductor technology, specifically to a memory device and a method for manufacturing the same. Memory devices with two-dimensional or planar structures have evolved to store more data in the same area using micro-patterning processes. However, as circuit line widths narrow due to the demand for high integration, they exhibit various limitations, such as performance degradation caused by intensified interference between memory cells. Of course, in addition to these structural limitations, there is also the problem that manufacturing costs inevitably rise because expensive equipment must be introduced to pattern fine line widths. A 3D memory device has been proposed as an alternative to overcome the limitations of 2D memory devices. The 3D memory device has the advantage of being able to realize more capacity in the same area by stacking memory cells vertically to increase the number of layers, and can provide high performance and excellent power efficiency. In order to independently apply electrical signals to electrode layers placed at different heights in a 3D memory device, contacts must be connected to each electrode layer, and various technologies are being developed for this purpose. FIG. 1 is a schematic plan view of a memory device according to one embodiment of the present invention. Figure 2 is a cross-sectional view along the A-A' line of Figure 1. Figure 3 is a cross-sectional view along the B-B' line of Figure 1. FIG. 4 is a cross-sectional view illustrating a memory device according to one embodiment of the present invention. FIG. 5 is a flowchart illustrating a method for manufacturing a memory device according to one embodiment of the present invention. FIGS. 6a to 6d are cross-sectional views illustrating a memory device according to an embodiment of the present invention in the manufacturing steps. FIGS. 7a to 7d are plan views illustrating a memory device according to an embodiment of the present invention in manufacturing steps. FIG. 8 is a plan view illustrating a memory device according to another embodiment of the present invention. Figure 9 is a cross-sectional view along the D-D' line of Figure 8. Figure 10 is a cross-sectional view along the line E-E' of Figure 8. FIG. 11 is a flowchart illustrating a method for manufacturing a memory device according to another embodiment of the present invention. FIGS. 12a to 12c are cross-sectional views illustrating a memory device according to another embodiment of the present invention in the manufacturing steps. FIG. 13a is a cross-sectional view illustrating a trench of a memory device according to another embodiment of the present invention. FIGS. 13b and FIGS. 13c are cross-sectional views illustrating a memory device according to another embodiment of the present invention. FIGS. 14 and 15 are plan views illustrating a memory device according to embodiments of the present invention. FIG. 16 is a block diagram schematically illustrating a memory system including a memory device according to the present invention. FIG. 17 is a block diagram schematically illustrating a computing system including a memory device according to the present invention. The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Furthermore, the shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the depicted details. Throughout the specification, the same reference numerals refer to the same components. Additionally, in describing the present invention, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of the present invention, such detailed description is omitted. Where terms such as 'comprising,' 'having,' or 'consisting of' are used in this specification, other parts may be added unless 'only' is used. Where a component is expressed in the singular, it may include a plural unless specifically stated otherwise. In addition, when interpreting the components in the embodiments of the present invention, they should be interpreted as including an error range even without separate explicit description. In addition, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the present invention. These terms are used merely to di