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KR-102960702-B1 - MEMORY SYSTEM, MEMORY CONTROLLER

KR102960702B1KR 102960702 B1KR102960702 B1KR 102960702B1KR-102960702-B1

Abstract

Embodiments of the present invention relate to a memory system and a memory controller. When an error occurs in target data stored in a target memory area, by setting the operation parameter of the power controller to a first operation parameter, which is one of a plurality of candidate operation parameters, the memory controller can stably operate the firmware and respond to firmware operation errors caused by changes in the external environment.

Inventors

  • 옥은재
  • 박성진

Assignees

  • 에스케이하이닉스 주식회사

Dates

Publication Date
20260507
Application Date
20191105

Claims (18)

  1. memory device; and It includes a memory controller that controls the above memory device, and The above memory controller is, Determine whether an error has occurred in the target data stored in the preset target memory area, and A memory system that, when an error occurs in the above target data, sets the operation parameter of a power controller that changes the magnitude of the power supplied to the memory controller from a power source located outside the memory controller from a first power level to a second power level to a first operation parameter, which is one of a plurality of preset candidate operation parameters.
  2. In paragraph 1, The above power controller is a memory system that is an LDO regulator.
  3. In paragraph 1, The above memory controller is, A memory system that determines that an error has occurred in the target data if an error occurs in the checksum of the target data.
  4. In paragraph 1, The above memory controller is, Determining whether to change the operation parameter of the power controller according to the total data light size for the first operation parameter, and A memory system in which the total data light size for the above-mentioned first operation parameter is determined by the sum of the data light sizes requested from the host from the first time point to the second time point.
  5. In paragraph 4, The first point in time is the point in time when the memory controller sets the operation parameter of the power controller to the first operation parameter, and A memory system in which the second point in time is the point in time when an error occurs in the target data or the point in time when the memory controller confirms the error that occurred in the target data.
  6. In paragraph 4, The above memory controller is, If the total data light size for the first operation parameter is less than a preset first size, A memory system that changes the operation parameter of the above power controller to a second operation parameter different from the first operation parameter among the plurality of candidate operation parameters.
  7. In paragraph 6, The above memory controller is, A memory system that determines whether to store the total data light size for the first operation parameter above in a preset history area.
  8. In Paragraph 7, The above memory controller is, A memory system that stores information about the total data light size for the first operation parameter in the history area if the total data light size for the first operation parameter is greater than or equal to a preset second size.
  9. In Paragraph 7, The above memory controller is, If the total data light size for all of the above candidate operation parameters is less than the first size, A memory system that sets the operation parameter of the above power controller to the candidate operation parameter among the above candidate operation parameters that has the maximum total data write size.
  10. In a memory controller that controls a power controller for changing the magnitude of power supplied from a power source from a first power level to a second power level, It includes a control circuit for setting the operation parameters of the above-mentioned power controller, and The above power controller controls the amount of power supplied to the memory controller, and The above control circuit is, Determine whether an error has occurred in the target data stored in the preset target memory area, and A memory controller that sets the operation parameter of the power controller to a first operation parameter, which is one of a plurality of preset candidate operation parameters, when an error occurs in the above target data.
  11. In Paragraph 10, The above power controller is a memory controller that is an LDO regulator.
  12. In Paragraph 10, The above control circuit is, A memory controller that determines that an error has occurred in the target data when an error occurs in the checksum of the target data.
  13. In Paragraph 10, The above control circuit is, Determining whether to change the operation parameter of the power controller according to the total data light size for the first operation parameter, and A memory controller in which the total data light size for the first operation parameter is determined as the sum of the data light sizes requested from the host from the first time point to the second time point.
  14. In Paragraph 13, The first point in time is the point in time when the control circuit sets the operation parameter of the power controller to the first operation parameter, and The above second point in time is a memory controller at the point in time when an error occurs in the target data or at the point in time when the control circuit confirms the error that occurred in the target data.
  15. In Paragraph 13, The above control circuit is, If the total data light size for the first operation parameter is less than a preset first size, A memory controller that changes the operation parameter of the above power controller to a second operation parameter different from the first operation parameter among the plurality of candidate operation parameters.
  16. In paragraph 15, The above control circuit is, A memory controller that determines whether to store the total data light size for the first operation parameter above in a preset history area.
  17. In Paragraph 16, The above control circuit is, A memory controller that stores information about the total data light size for the first operation parameter in the history area if the total data light size for the first operation parameter is greater than or equal to a preset second size.
  18. In Paragraph 16, The above control circuit is, If the total data light size for all of the above candidate operation parameters is less than the first size, A memory controller that sets the operation parameter of the above power controller to the candidate operation parameter among the above candidate operation parameters that has the maximum total data write size.

Description

Memory System and Memory Controller {MEMORY SYSTEM, MEMORY CONTROLLER} Embodiments of the present invention relate to a memory system and a memory controller. A memory system corresponding to a storage device is a device that stores data based on requests from a host, such as a computer, mobile terminals like smartphones and tablets, or various electronic devices. A memory system may include not only devices that store data on magnetic disks, such as a hard disk drive (HDD), but also devices that store data in non-volatile memory, such as a solid-state drive (SSD), Universal Flash Storage (UFS) device, and embedded MMC (eMMC) device. The memory system may further include a memory controller for controlling memory devices, and such a memory controller may receive a command from a host and, based on the received command, execute or control operations to read, write, or erase data in volatile or non-volatile memory included in the memory system. Additionally, the memory controller may drive firmware to perform logical operations for executing or controlling these operations. The memory controller receives power from an external power source to run the aforementioned firmware through an internal processor. Whether the memory controller can run the firmware stably depends on the state of the power supplied from the external power source. FIG. 1 is a schematic diagram of a memory system according to embodiments of the present invention. FIG. 2 is a block diagram schematically showing a memory device according to embodiments of the present invention. FIG. 3 is a schematic diagram showing each memory block of a memory device according to embodiments of the present invention. FIG. 4 is a diagram showing the structure of a word line and a bit line of a memory device according to embodiments of the present invention. FIG. 5 is a diagram schematically illustrating the operation of a memory system according to embodiments of the present invention. Figure 6 is a diagram showing an example of an LDO regulator. Figure 7 is a diagram showing another example of an LDO regulator. FIG. 8 is a flowchart illustrating the operation of determining the operation parameters of a power controller in a memory system according to embodiments of the present invention. FIG. 9 is a diagram showing an example of an operation to calculate the total data light size in a memory system according to embodiments of the present invention. FIG. 10 is a flowchart illustrating an example of the operation of a memory system according to embodiments of the present invention. FIG. 11 is a diagram illustrating the operation of selecting operation parameters of a power controller in a memory system according to embodiments of the present invention. FIG. 12 is a flowchart illustrating an example of the operation of a memory system according to embodiments of the present invention. FIG. 13 is a flowchart illustrating an example of a method of operation of a memory controller according to embodiments of the present invention. FIG. 14 is a configuration diagram of a computing system according to embodiments of the present invention. Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. FIG. 1 is a schematic diagram of a memory system (100) according to embodiments of the present invention. Referring to FIG. 1, a memory system (100) according to embodiments of the present invention may include a memory device (110) for storing data and a memory controller (120) for controlling the memory device (110). The memory device (110) includes a plurality of memory blocks and operates in response to the control of the memory controller (120). Here, the operation of the memory device (110) may include, for example, a read operation, a program operation (also called a "write operation"), and an erase operation. A memory device (110) may include a memory cell array comprising a plurality of memory cells (also simply called "cells") that store data. Such a memory cell array may exist within a memory block. For example, the memory device (110) can be implemented in various types such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), NAND Flash Memory, 3D NAND Flash Memory, NOR Flash Memory, Resistive Random Access Memory (RRAM), Phase-Change Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or Spin Transfer Torque Random Access Memory (STT-RAM). Meanwhile, the memory device (110) can be implemented as a three-dimensional array structure. Embodiments of the present invention can be applied to a flash memory device in which the charge storage layer is composed of a conductive floating gate, as well as to a charge trap flash (CTF) in which the charge storage layer is composed of an insu