KR-102961132-B1 - Method for manufacturing HBM by sequential application of W2W and D2W hybrid bonding processes

Abstract

The present invention relates to a method for manufacturing HBM, and more specifically, to a method for manufacturing HBM by sequentially applying W2W and D2W hybrid bonding processes, wherein at least two layers of core die wafers are produced by applying a W2W hybrid bonding process, at least two layers of good core dies are obtained and prepared through dicing, and at least two layers of good core dies are stacked on the base die wafer by applying a D2W hybrid bonding process to manufacture HBM, thereby shortening the HBM manufacturing time through the D2W hybrid bonding process to improve productivity and production efficiency, and reducing the defect rate of HBM by applying only at least two layers of good core dies. The means constituting the method for manufacturing an HBM by sequentially applying a W2W and D2W hybrid bonding process according to the present invention is characterized by comprising: a core die wafer manufacturing step of manufacturing at least two core die wafers by applying a W2W hybrid bonding process; a step of obtaining and preparing at least two core dies of good quality from the at least two core die wafers to apply a D2W hybrid bonding process; a base die wafer preparation step for applying the D2W hybrid bonding process; and a core die stacking step of stacking at least two core dies of good quality onto the base die wafer by applying the D2W hybrid bonding process in a set number of layers.

Inventors

• 이상호

Assignees

• 엠디바이스 주식회사

Dates

Publication Date

20260507

Application Date

20250210

Claims (3)

1. A method for manufacturing High Bandwidth Memory (HBM) through a Die-to-Wafer (D2W) hybrid bonding process, wherein the core dies applied to the Die-to-Wafer (D2W) hybrid bonding process are formed in at least two layers, and the at least two layers of core dies are manufactured through a Wafer-to-Wafer (W2W) hybrid bonding process. A core die wafer fabrication step of fabricating at least two core die wafers by applying a W2W (Wafer to Wafer) hybrid bonding process; A step of acquiring and preparing at least two sets of good core dies for applying a D2W (Die to Wafer) hybrid bonding process from the above at least two sets of core die wafers; A base die wafer preparation step for applying the above D2W (Die to Wafer) hybrid bonding process; A method for manufacturing HBM (High Bandwidth Memory) by sequentially applying W2W (Wafer to Wafer) and D2W (Die to Wafer) hybrid bonding processes, characterized by comprising a core die stacking step of stacking at least two or more core dies of the good product onto a base die wafer in a set number of layers by applying the above D2W (Die to Wafer) hybrid bonding process.
2. In claim 1, The above core die wafer fabrication step is, A method for manufacturing High Bandwidth Memory (HBM) by sequentially applying a Wafer-to-Wafer (W2W) and Die-to-Wafer (D2W) hybrid bonding process, characterized by comprising: a process of preparing at least two core die wafers; a process of performing a Chemical Mechanical Polishing (CMP) process and a cleaning process for each core die wafer; an activation and cleaning process in which an activation process is performed on the dielectric surfaces of the core die wafers to be bonded, followed by a cleaning process; a dielectric bonding process in which the activated dielectric surfaces of the core die wafers to be bonded are aligned and bonded to perform dielectric bonding; a process of repeating the activation and cleaning process and the dielectric bonding process until the core die wafers are stacked by a predetermined number of layers to form at least two layers of dielectric-bonded core die wafers; and a process of annealing the at least two layers of dielectric-bonded core die wafers to perform metal bonding.
3. In claim 1, The above core die stacking step is, A process of performing a Chemical Mechanical Polishing (CMP) process and a cleaning process on a prepared base die wafer; a process of performing a cleaning process after performing an activation process on the dielectric surfaces of at least two core dies to be bonded with the base die wafer; a basic dielectric bonding process of performing dielectric bonding by aligning and joining the activated dielectric surfaces of the base die wafer and the at least two core dies to be bonded; an additional activation and cleaning process of performing a cleaning process after performing an activation process on the dielectric surfaces of the at least two core dies to be additionally bonded with the dielectric-bonded at least two core dies; an additional dielectric bonding process of performing dielectric bonding by aligning and joining the activated dielectric surfaces of the at least two core dies to be bonded with the bonded at least two core dies; and repeating the additional activation and cleaning process and the additional dielectric bonding process until the at least two core dies are stacked on the base die wafer by a predetermined number of layers, thereby forming a base die A method for manufacturing High Bandwidth Memory (HBM) by sequentially applying a Wafer-to-Wafer (W2W) and Die-to-Wafer (D2W) hybrid bonding process, characterized by comprising the steps of forming at least two layers of core dies stacked by dielectric bonding on a wafer and performing metal bonding by annealing the at least two layers of core dies stacked by dielectric bonding on the base die wafer.

Description

Method for manufacturing HBM by sequential application of W2W and D2W hybrid bonding processes The present invention relates to a method for manufacturing HBM, and more specifically, to a method for manufacturing HBM by sequentially applying W2W and D2W hybrid bonding processes, wherein at least two layers of core die wafers are produced by applying a W2W hybrid bonding process, at least two layers of good core dies are obtained and prepared through dicing, and at least two layers of good core dies are stacked on the base die wafer by applying a D2W hybrid bonding process to manufacture HBM, thereby shortening the HBM manufacturing time through the D2W hybrid bonding process to improve productivity and production efficiency, and reducing the defect rate of HBM by applying only at least two layers of good core dies. Semiconductor technology is evolving into a heterogeneous technology trend. Heterogeneous semiconductor technology refers to the technology that integrates various types of semiconductor materials and technologies to form a single system. This enables the achievement of performance, power efficiency, and cost optimization, and plays a crucial role in the field of next-generation AI semiconductors. In the packaging domain, heterogeneous semiconductor technologies include chiplet architecture and 2.5D and 3D stacking technologies. Chiplet architecture modularizes individually designed chips to be implemented in the form of a System On Package (SoP) instead of a System On Chip (SoC), and is a technology that efficiently integrates components such as CPUs, GPUs, and memory by manufacturing them using optimized processes. 2.5D and 3D stacking refers to stacking into 2.5-dimensional or 3-dimensional structures using technologies such as TSV (Through Silicon Via) and hybrid bonding, and is a technology that efficiently connects chips with different functions (processors, memory, sensors, etc.) to increase network bandwidth and energy efficiency. In response to the demand for miniaturization and lightweighting of electronic devices, the semiconductor industry is pursuing the miniaturization, lightweighting, and thinning of semiconductor packages mounted on electronic devices, while simultaneously increasing their speed, multifunctionality, and capacity. Consequently, there is a growing need for packaging technologies capable of storing more data and transmitting data at higher speeds. High Bandwidth Memory (HBM) is a well-known such technology, as it enables high-level bandwidth by stacking more DRAMs on a substrate of the same area. HBM is manufactured by stacking multiple memory chips. One of the stacking methods used is hybrid bonding. It is distinguished from TC bonding (Thermo-Compression), which mechanically bonds using heat and pressure, in that it bonds using both mechanical and electrical methods. “Unlike TC bonding, which utilizes heat and pressure, hybrid bonding eliminates the cross-linking between chips and allows them to be directly stacked.” Production using TC bonding requires a cross-linking mechanism called a bumper. Hybrid bonding does not require cross-linking because it directly connects the two chips. Hybrid bonding can be classified into W2W hybrid bonding processes and D2W hybrid bonding processes depending on the types of materials joined vertically. The W2W (Wafer to Wafer) hybrid bonding process is a method of bonding wafers together and is applied to image sensors (CIS) and 3D NAND. The process is performed with the entire chip (die) connected at the wafer level; the bonding surface is prepared through chemical activation and cleaning of the wafer surface, and the two wafers are aligned before bonding. The W2W hybrid bonding process is suitable for mass production and facilitates easy alignment between wafers, but the inclusion of defective chips can affect the overall wafer production yield. The D2W (Die to Wafer) hybrid bonding process involves bonding dies onto a wafer and is applied to SRAM-on-Logic. It involves continuously stacking dies on a wafer and is representatively applied to HBM. Individual chips (dies) are moved to a carrier, followed by activation and cleaning processes. A bonder is then used to directly place the individual chips onto a target wafer, performing bonding sequentially one by one. While this method offers high flexibility due to the ability to perform precise bonding at the chip level, it has the disadvantage of being time-consuming, making it unsuitable for mass production. Therefore, while manufacturing HBM through a Die-to-Wafer (D2W) hybrid bonding process offers significant efficiency and flexibility in the bonding process itself, it has the disadvantage of requiring unnecessarily long manufacturing times and consequently reducing productivity and production efficiency because individual chips must be stacked sequentially one by one. Accordingly, there is a need to propose a manufacturing method that can improve productivity, production effici