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KR-102961155-B1 - Gold Through Silicon Mask Plating

KR102961155B1KR 102961155 B1KR102961155 B1KR 102961155B1KR-102961155-B1

Abstract

Systems and methods for an EAG-TSM (etch-assisted gold (Au) through silicon mask) plating method are provided. An exemplary method comprises the steps of providing a seed layer on a substrate and providing a silicon mask on at least a portion of the seed layer on the substrate. The silicon mask comprises one or more vias to be filled with Au. The masked substrate is processed in at least one processing cycle, each processing cycle comprising an Au plating sub-step and an etching sub-step. The cycles are repeated until a selected via filling thickness is achieved.

Inventors

  • 추아, 리 펑
  • 리앙, 데푸
  • 블리켄스더퍼, 제이콥 커티스
  • 포누스와미, 토마스 에이.
  • 버커루, 브라이언 엘.
  • 메이어, 스티븐 티.

Assignees

  • 램 리써치 코포레이션

Dates

Publication Date
20260508
Application Date
20200213
Priority Date
20190214

Claims (15)

  1. In the EAG-TSM (etch assisted gold (Au) through silicon mask) plating method, A step of providing a seed layer on a substrate; A step of providing a silicon mask on at least a portion of the seed layer on the substrate, wherein the silicon mask comprises one or more vias to be filled with Au; A step of processing the masked substrate in at least one processing cycle (subject), wherein each processing cycle comprises an Au plating sub-step and an etching processing sub-step; and The method includes the step of repeating the at least one processing cycle a number of times equal to the number of repetition cycles until a selected via filling thickness is achieved. In each Au plating sub-step, Au residue is deposited on a silicon mask along with Au deposition in one or more vias, and the Au residue partially blocks one or more vias; In each etching process sub-step, Au residue deposited on the silicon mask is etched to remove blockage of one or more vias for Au deposition in one or more vias in the Au plating sub-step of a subsequent processing cycle, EAG-TSM plating method.
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  3. In Article 1, An EAG-TSM plating method comprising a step of generating via-filling efficiency based on via filling degree versus Au residual degree.
  4. In Paragraph 3, An EAG-TSM plating method further comprising a step of adjusting the via-filling efficiency based on the inclusion of sulfur trioxide ( SO₃ ) in the chemical composition of the Au plating solution in the plating sub-step.
  5. In Paragraph 3, An EAG-TSM plating method further comprising a step of adjusting the via-filling efficiency based on the inclusion of cyanide (CN) in the chemical composition of the Au plating solution in the plating sub-step.
  6. In Article 1, An EAG-TSM plating method in which the etchant of the above etching process sub-step comprises I-/I2 in a 6:1 molar ratio.
  7. In Article 1, An EAG-TSM plating method in which the etchant of the above etching treatment sub-step comprises aqua regia with a molar ratio of nitric acid to hydrochloric acid of 1:3.
  8. In Article 1, An EAG-TSM plating method in which the cycle time of the first cycle in the above-mentioned number of repeated cycles is the same as the cycle time of another cycle in the above-mentioned number of repeated cycles.
  9. In Article 1, An EAG-TSM plating method in which the cycle time of the first cycle in the above-mentioned number of repeated cycles is not the same as the cycle time of another cycle in the above-mentioned number of repeated cycles.
  10. In Article 1, An EAG-TSM plating method in which the frequency of applying the etching treatment sub-step during a first period of treating the masked substrate in a first cycle of the plurality of repeated cycles is different from the frequency of applying the etching treatment sub-step during a second period of treating the masked substrate in a different cycle of the plurality of repeated cycles.
  11. In a plating system for the EAG-TSM (etch assisted gold (Au) through silicon mask) plating method, Cathode; Anode; An in-situ substrate processing module configured to perform alternating sub-steps of at least one processing cycle, wherein the sub-steps include an Au plating sub-step and an etching processing sub-step, and the processing module is common to each of the sub-step operations; A robot for receiving a substrate or transferring it to a processing module, wherein the substrate comprises a seed layer and a silicon mask on at least a portion of the seed layer on the substrate, and the silicon mask comprises one or more vias to be filled with Au by the plating system; Substrate holder; and It includes an etchant delivery means operable to deliver an etchant during the above etching process sub-step, and In each Au plating sub-step, Au residue is deposited on a silicon mask along with Au deposition in one or more vias, and the Au residue partially blocks one or more vias; In each etching process sub-step, Au residue deposited on the silicon mask is etched to remove blockage of one or more vias for Au deposition in one or more vias in the Au plating sub-step of a subsequent processing cycle, Plating system.
  12. In Article 11, The substrate holder is operable to lower the substrate into the Au plating solution within the processing module during the Au plating sub-step and to withdraw the substrate from the plating solution after the Au plating sub-step. A plating system in which the substrate holder is further operable to hold the substrate in the path of the etchant during the etching process sub-step while the substrate holder is in the drawn-out position.
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  14. In Article 12, A plating system configured such that the processing module repeats the at least one processing cycle until a selected via filling thickness is achieved.
  15. In Article 12, A plating system configured such that the substrate holder applies a selected substrate rotation speed during at least the etching process sub-step.

Description

Gold Through Silicon Mask Plating The present disclosure generally relates to gold through silicon mask (TSM) plating for substrate processing in semiconductor manufacturing, particularly. The description of the background technology provided in this specification is generally intended to provide context for the present disclosure. To the extent described in this background technology section, the work of the inventors named herein, as well as aspects of the technology that may not otherwise be recognized as prior art at the time of filing, are not explicitly or implicitly recognized as prior art for the present disclosure. The formation of metal structures on a micron scale is most commonly accomplished by plating operations performed using one or more pre-patterned sacrificial masks. One method employs an organic photoresist mask. This method is generally referred to as through-resist plating. Some manufacturers in the Wafer Level Packaging (WLP) industry widely use these methods to form copper (Cu) and gold (Au) redistribution layers (RDLs), flip-chip bump interconnects of Cu, nickel (Ni), and tin (Sn) alloy solders, and to perform Au bumping. Much more complex structures, such as those found in Micro-Electro-Mechanical Systems (MEMS) applications, also utilize through-resist plating technology. While offering other options, TSM plating using Au also presents several serious challenges. Au metal is easily deposited spuriously on the Si mask, and even more so at via openings. These unwanted Au depositions on the Si continue to grow, often growing more strongly at the via entrances, which can degrade the desired Au via filling plating patterns. Eventually, the via entrance or at least a portion of the via entrance becomes substantially closed. This may prevent the Au via from being fully filled prematurely. These defective, partially filled vias are colloquially referred to as voids, and depending on the nature of the closure, these voids can be of various shapes, sizes, and locations. Claim of priority This application claims the advantage of priority to U.S. Provisional Application No. 62/805,604 by Chua et al., filed on February 14, 2019, titled “Gold Through Silicon Mask Plating,” the entirety of which is incorporated herein by reference. The present disclosure aims to address at least some of the difficulties discussed above. The present disclosure provides exemplary methods for gold (Au) TSM plating. Here, TSM is distinguished from TSV (Through Silicon Via) methods in that in TSM, Si is typically a sacrificial layer placed over a metal seed layer, and this deposition is intended to occur only in the vias. However, a significant amount of gold deposition still occurs on the Si field, typically more severely at the via entrance. Such spurious deposition is undesirable, and in some examples, the closure of the via entrance may interrupt the Au via filling process. Such interruption may result in or leave defective structures or partial fillings and/or voids, and highly non-uniform via filling. These and other issues are addressed in some examples by a cyclic deposition-etching process, also referred to herein as EAG-TSM (Etch Assisted Gold Through Silicon Mask). This process minimizes Si field plating in some examples and maintains via entrance integrity, enabling complete via filling and removal of closed voids, especially in high aspect ratio structures. Accordingly, in some examples, an EAG-TSM (etch assisted gold (Au) through silicon mask) plating method comprises the steps of: providing a seed layer on a substrate; providing a silicon mask on at least a portion of the seed layer on the substrate, wherein the silicon mask comprises one or more vias to be filled with Au; processing the masked substrate in at least one processing cycle, wherein each processing cycle comprises an Au plating sub-step and an etching sub-step; and repeating the at least one processing cycle until a selected via filling thickness is achieved. In some examples, Au residue deposited adjacent to the via by the plating sub-step is removed by the etching sub-step. In some examples, via-filling efficiency is based on the degree of via filling versus the degree of Au residue. Some examples further include a step of adjusting the via-filling efficiency based on the inclusion of sulfur trioxide ( SO₃ ) in the chemicals of the Au plating solution in the plating sub-step. Some examples further include adjusting the via-filling efficiency based on the inclusion of cyanide (CN) in the chemicals of the Au plating solution in the plating sub-step. In some examples, the etchant for the etching process sub-step comprises I-/I2 in a 6:1 molar ratio. In some examples, the etchant for the etching process sub-step comprises aqua regia in a 1:3 molar ratio. In some examples, the cycle time of the first cycle in at least one cycle is the same as the cycle time of the second cycle in at least one cycle. In some examples, the cycle time of the fir