KR-102961254-B1 - Semiconductor Package and Manufacturing Method Thereof

KR102961254B1KR 102961254 B1KR102961254 B1KR 102961254B1KR-102961254-B1

Abstract

The present invention relates to a semiconductor package comprising: 1 substrate; a plurality of semiconductor chips disposed on the first substrate; and a connecting structure disposed between at least one semiconductor chip among the plurality of semiconductor chips and the first substrate, and electrically connecting at least two semiconductor chips arranged in a horizontal direction among the plurality of semiconductor chips, wherein the connecting structure comprises a conductive layer directly connected to the semiconductor chip, a plurality of connecting members electrically connected to the first substrate, and a wiring layer disposed between the conductive layer and the plurality of connecting members.

Inventors

임재성
김동현
장주환
김광일
장용규

Assignees

하나 마이크론(주)

Dates

Publication Date: 20260512
Application Date: 20240322
Priority Date: 20230404

Claims (20)

First substrate; A plurality of semiconductor chips disposed on the first substrate; and A connecting structure disposed between at least one semiconductor chip among the plurality of semiconductor chips and the first substrate, and electrically connecting at least two semiconductor chips arranged in a horizontal direction among the plurality of semiconductor chips, The above connecting structure includes a conductive layer directly connected to a plurality of irregular bumps formed on the lower part of the semiconductor chip, a plurality of connecting members electrically connected to the first substrate, and a wiring layer disposed between the conductive layer and the plurality of connecting members. The conductive layer comprises a plurality of second fillers and a first insulating material coated between the plurality of second fillers, and The plurality of second fillers are formed to have different pitches to correspond to the arrangement of the plurality of irregular bumps, and A semiconductor package characterized in that each second filler is formed such that the upper cross-sectional area is larger than the lower cross-sectional area.
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In paragraph 1, A semiconductor package characterized in that the wiring layer comprises a wiring circuit and a second insulating material coated on the wiring circuit.
In paragraph 3, A semiconductor package characterized in that the first and second insulating materials are formed from a dielectric or polymer material.
In paragraph 1, A semiconductor package characterized in that the wiring layer is manufactured by filling copper (Cu) by an electroplating method using a Damascene process or printed in the form of a redistribution layer (RDL).
In paragraph 1, A semiconductor package characterized in that the above connecting structure is formed from a silicon wafer, an active die, or an Integrated Passive Device (IPD).
In paragraph 1, A semiconductor package characterized in that the above connecting structure electrically connects the first substrate and at least one semiconductor chip among the plurality of semiconductor chips.
In paragraph 1, A semiconductor package characterized in that the above connecting structure is mounted on the upper surface of the first substrate in a flip-chip structure.
In paragraph 1, A semiconductor package characterized in that the connecting structure is formed to have an area smaller than the sum of the areas of the semiconductor chips combined with the connecting structure.
In Paragraph 9, A semiconductor package further comprising a plurality of first fillers disposed between the first substrate and at least one of the plurality of semiconductor chips, electrically connecting the first substrate and the at least one semiconductor chip.
In Paragraph 10, A semiconductor package characterized in that each first filler is formed such that the width of the cross-sectional area is constant or the width of the cross-sectional area gradually increases as it moves upward.
In Paragraph 9, A semiconductor package further comprising a plurality of vertical wires disposed between the first substrate and at least one of the plurality of semiconductor chips, electrically connecting the first substrate and the at least one semiconductor chip.
In paragraph 1, A semiconductor package characterized in that the connecting structure is formed to have an area equal to or larger than the sum of the areas of all semiconductor chips combined with the connecting structure.
In paragraph 1, A semiconductor package characterized in that the first substrate has a cavity structure for mounting the connecting structure.
In paragraph 1, A semiconductor package further comprising a heat dissipation die disposed on at least one of the plurality of semiconductor chips.
In paragraph 15, A semiconductor package further comprising a thermal interface material (TIM) disposed between at least one semiconductor chip and the heat dissipation die or disposed on the upper surface of the heat dissipation die.
In paragraph 1, A semiconductor package characterized in that the plurality of semiconductor chips described above include one or more logic chips and one or more memory chips.
Step of manufacturing a connecting structure; A step of arranging a plurality of first fillers on a first substrate; A step of mounting the connecting structure in an adjacent area of the plurality of first fillers; A step of placing a molding member on the first substrate, the plurality of first fillers, and the connecting structure; A step of removing the upper region of the molding member and the second substrate of the connecting structure so that the plurality of first fillers and the conductive layer of the connecting structure are exposed to the outside; and The method includes the step of mounting a plurality of semiconductor chips on the plurality of first fillers and the connecting structure, wherein The step of manufacturing the above connecting structure is, A step of forming a conductive layer on the second substrate; A step of forming a wiring layer on the conductive layer; and A method for manufacturing a semiconductor package comprising the step of arranging a plurality of connection members on the wiring layer.
Step of manufacturing a connecting structure; A step of mounting the connecting structure on the first substrate; A step of placing a molding member on the first substrate and the connecting structure; A step of removing the upper region of the molding member and the second substrate of the connecting structure so that the conductive layer of the connecting structure is exposed to the outside; and The method includes the step of mounting a plurality of semiconductor chips on a connecting structure having the above-mentioned conductive layer exposed, The step of manufacturing the above connecting structure is, A step of forming a conductive layer on the second substrate; A step of forming a wiring layer on the conductive layer; and A method for manufacturing a semiconductor package comprising the step of arranging a plurality of connection members on the wiring layer.
In paragraph 18 or 19, The conductive layer comprises a plurality of second fillers and a first insulating material coated between the plurality of second fillers, and A method for manufacturing a semiconductor package, characterized in that each second filler is formed such that the upper cross-sectional area is larger than the lower cross-sectional area.

Description

Semiconductor Package and Manufacturing Method Thereof The present invention relates to a semiconductor package and a method for manufacturing the same, and more specifically, to a semiconductor package and a method for manufacturing the same that enables miniaturization and further reduces manufacturing costs. A semiconductor chip refers to an integrated circuit composed of semiconductors, which have electrical conductivity higher than insulators but lower than conductors. Typically, after a semiconductor chip is separated from a wafer, which is a single-crystal substrate, a type of packaging process is required. This is intended to protect the chip from physical shock and to mitigate the difference in integration density between the chip and the substrate on which it will be mounted, thereby increasing ease of mounting. The resulting packaged semiconductor chip is called a semiconductor package. Multiple semiconductor chips can be mounted in such semiconductor packages, and depending on the arrangement of the mounted semiconductor chips, they can be classified into 2D, 2.5D, 3D, etc. Among these, a 2.5D semiconductor package refers to a package in which logic chips are arranged horizontally and memory chips are stacked vertically. In addition, in a 2.5D semiconductor package, an interposer or a bridge die may be provided between the substrate and the semiconductor chip to increase the connection rate between the substrate and the semiconductor chip (i.e., the die). In such a case, the semiconductor chip is electrically connected to the substrate through the interposer or the bridge die. However, conventional interposers or bridge dies have the problem of being somewhat expensive to manufacture and disadvantageous in terms of miniaturization of semiconductor packages. Therefore, a method to solve these problems is required. FIG. 1a is a drawing showing the structure of a semiconductor package according to a first embodiment of the present invention; FIG. 1b is a drawing showing the structure of the connecting structure illustrated in FIG. 1a; FIG. 2 is a flowchart illustrating a method for manufacturing a semiconductor package according to a first embodiment of the present invention; FIGS. 3a to 3g are drawings referenced to explain a method for manufacturing a semiconductor package according to a first embodiment of the present invention; FIG. 4a is a drawing showing the structure of a semiconductor package according to a second embodiment of the present invention; FIG. 4b is a drawing showing the structure of the connecting structure illustrated in FIG. 4a; FIG. 5 is a flowchart illustrating a method for manufacturing a semiconductor package according to a second embodiment of the present invention; FIGS. 6a to 6g are drawings referenced to explain a method for manufacturing a semiconductor package according to a second embodiment of the present invention; FIG. 7 is a drawing showing the structure of a semiconductor package according to a third embodiment of the present invention; FIG. 8 is a drawing showing the structure of a semiconductor package according to a fourth embodiment of the present invention; FIG. 9 is a drawing showing the structure of a semiconductor package according to a fifth embodiment of the present invention; FIG. 10 is a flowchart illustrating a method for manufacturing a connecting structure according to an embodiment of the present invention; FIGS. 11a to 11h are drawings referenced to explain a method for manufacturing a connecting structure according to an embodiment of the present invention; FIG. 12 is a flowchart illustrating a method for manufacturing a connecting structure according to another embodiment of the present invention; FIGS. 13a to 13g are drawings referenced to explain a method for manufacturing a connecting structure according to another embodiment of the present invention. Hereinafter, embodiments disclosed in this specification will be described in detail with reference to the attached drawings. Identical or similar components regardless of drawing symbols are assigned the same reference number, and redundant descriptions thereof will be omitted. In the following description of embodiments according to the present invention, where each layer (film), region, pattern, or structure is described as being formed "on" or "under" of a substrate, each layer (film), region, pad, or pattern, "on" and "under" include both being formed "directly" and "indirectly" through another layer. Furthermore, the reference for the "on" or "under" of each layer is described based on the drawings. In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically depicted for convenience and clarity of explanation. Also, the size of each component does not entirely reflect its actual size. Identical drawing symbols refer to identical components. In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected,"