KR-102961300-B1 - Method for manufacturing GaN HEMT power semiconductor epitaxial wafers with high-quality GaN channel region through growth temperature modulation

Abstract

A method for manufacturing a GaN HEMT power semiconductor epitaxy wafer having a high-quality GaN channel region through growth temperature modulation disclosed comprises: a step of growing an AlN nucleation region formed on a growth substrate; a step of growing a first GaN channel region formed on the AlN nucleation region at a first growth temperature greater than or equal to the growth temperature of the AlN nucleation region; a step of growing a second GaN channel region formed on the first GaN channel region at a second growth temperature less than the first growth temperature; a step of growing a third GaN channel region formed on the second GaN channel region at a third growth temperature equal to or greater than the first growth temperature; and a step of forming an AlGaN barrier region on the third GaN channel region.

Inventors

• 송준오
• 임현철
• 한영훈
• 윤형선

Assignees

• 웨이브로드 주식회사

Dates

Publication Date

20260513

Application Date

20250203

Priority Date

20240412

Claims (9)

1. A step of forming on a growth substrate and growing an AlN nucleation region; A step of forming a first GaN channel region on the above AlN nucleation region and growing the first GaN channel region at a first growth temperature greater than or equal to the growth temperature of the above AlN nucleation region; A step of forming a second GaN channel region on the first GaN channel region and growing the second GaN channel region at a second growth temperature lower than the first growth temperature; A step of forming a third GaN channel region on the second GaN channel region and growing the third GaN channel region at a third growth temperature equal to or higher than the first growth temperature; A step of forming an AlGaN barrier region on the third GaN channel region; and A method for manufacturing a GaN HEMT power semiconductor epitaxy wafer having a high-quality GaN channel region through growth temperature modulation, comprising the step of forming a SiNx region that is formed to be inserted between the first GaN channel region and the second GaN channel region, stopping the growth of the first GaN channel region and masking crystal defects on the surface of the first GaN channel region.
2. In claim 1, A method for manufacturing a GaN HEMT power semiconductor epitaxy wafer having a high-quality GaN channel region through growth temperature modulation, comprising the step of growing an MT-GaN channel region at an MT growth temperature that is greater than or equal to the second growth temperature and less than the third growth temperature, wherein the MT-GaN channel region is formed to be inserted between the second GaN channel region and the third GaN channel region.
3. delete
4. In claim 1, A method for manufacturing a GaN HEMT power semiconductor epitaxy wafer having a high-quality GaN channel region through growth temperature modulation, wherein the step of forming the above SiNx region involves stopping the growth of the first GaN channel region and forming nanoscale SiNx in a 3 -dimensional growth mode by supplying a Si source, SiH4 or Si2H6 , under conditions where a nitrogen source, ammonia (NH3), is supplied.
5. In claim 1, The step of growing the above AlN nucleation region is, A first nucleation region growth step in which only TMAl or TEAl, an Al source, is supplied without supplying ammonia ( NH₃ ), a nitrogen source, at a temperature lower than the growth temperature of the above AlN nucleation region; A second nucleation region growth stage that supplies ammonia ( NH₃ ), a nitrogen source, to the first nucleation region growth stage and grows AlN in a 3D growth mode (3-dimensional growth mode); and A method for manufacturing a GaN HEMT power semiconductor epitaxy wafer having a high-quality GaN channel region through growth temperature modulation, comprising: a third nucleation region growth step of raising the temperature to the growth temperature of the above AlN nucleation region and growing AlN in a 2D growth mode (2-dimensional growth mode).
6. In claim 1, A method for manufacturing a GaN HEMT power semiconductor epitaxy wafer having a high-quality GaN channel region through growth temperature modulation, wherein the step of growing the first GaN channel region is to grow GaN in a 2D growth mode (2-dimensional growth mode) at the first growth temperature.
7. In claim 1, The step of growing the second GaN channel region is a method for manufacturing a GaN HEMT power semiconductor epitaxy wafer having a high-quality GaN channel region through growth temperature modulation, which relieves stress caused by the first growth temperature, which is high temperature, during the growth of the first GaN channel region, increases thickness, and minimizes crystal defects.
8. In claim 2, The step of growing the third GaN channel region is a method for manufacturing a GaN HEMT power semiconductor epitaxy wafer having a high-quality GaN channel region through growth temperature modulation, which improves the crystallinity of the first, second, and third GaN channel regions or the entire first, second, MT, and third GaN channel regions.
9. In claim 2, The first growth temperature above is 1050~1100℃, and The above second growth temperature is 750~850℃, and The above third growth temperature is 1050~1100℃, and A method for manufacturing a GaN HEMT power semiconductor epitaxy wafer having a high-quality GaN channel region through growth temperature modulation, wherein the above MT growth temperature is 850~950℃.

Description

Method for manufacturing GaN HEMT power semiconductor epitaxial wafers with high-quality GaN channel region through growth temperature modulation The present invention relates to a method for manufacturing a GaN HEMT power semiconductor epitaxy wafer, characterized by significantly improving the performance and quality of a GaN HEMT power semiconductor device by reducing crystal defects in the channel region and minimizing leakage current in the vertical or horizontal direction, and to a method for manufacturing a GaN HEMT power semiconductor epitaxy wafer having a high-quality GaN channel region through growth temperature modulation. The epitaxy structure of a GaN HEMT power semiconductor typically has a structure in which a nucleation region, a stress-relieving region, a buffer region, a channel region, and a barrier region are sequentially stacked on a growth substrate. The channel region and barrier region function as key active regions of GaN HEMT power semiconductor devices. In the active region, a horizontal channel with a high electron density of 2DEG ( 2- dimensional electron gas) is formed due to the polarization phenomenon of the group 3 nitride semiconductor, even without intentional dopant doping at the interface of the GaN channel region, which has a small energy bandgap in the Al 1-y Ga y N (barrier)/GaN (channel) hetero-junction. The polarization intensity is determined by the Al composition of Al 1-y Ga y N and the thickness of Al 1-y Ga y N, and typically the thickness is controlled according to the Al composition. In some cases, before growing an Al 1-y Ga y N barrier region on top of a GaN channel region, it is possible to introduce an AlN thin film with a thickness of less than 5 nm. Depending on the case, a capping region or a p-type group 3 nitride (GaN, AlGaN, AlInN, AlGaInN) thin film can be grown on top of the Al 1-y Ga y N barrier region. The substructure, consisting of a nucleation region, a stress-relieving region, and a buffer region, is provided to minimize crystal defects in the active region, prevent leakage current, and enable effective heat dissipation. The nucleation region is a region that promotes the formation of high-quality buffer regions and active regions, and it is proposed to be formed of AlN. The stress-relieving region is a region that prevents wafer warping or cracking caused by the subsequently grown buffer region and active region, and it is proposed to control the composition of gallium (Ga). The buffer region is a current blocking region that reduces vertical leakage current by having high-resistive properties, and achieves a specific purpose using a GaN material (C- or Fe-doped GaN) doped with carbon (C) or iron (Fe), etc., as a dopant. However, growing C- or Fe-doped GaN results in a degradation of GaN crystal quality, and since it is formed thickly to achieve high resistance properties, it hinders heat dissipation generated during the operation of GaN HEMT power semiconductor devices, thereby degrading device characteristics. Therefore, there is a need to develop a buffer region that possesses excellent heat dissipation performance while having crystal quality and high resistance properties. FIG. 1 is a drawing for explaining a method for manufacturing a GaN HEMT power semiconductor epitaxy wafer according to one embodiment of the present invention. Figure 2 is a drawing showing a modified example of Figure 1. FIG. 3 is a drawing for explaining a method for manufacturing a GaN HEMT power semiconductor epitaxy wafer according to another embodiment of the present invention. Figure 4 is a drawing showing a modified example of Figure 3. Figure 5 is a diagram illustrating the method of manufacturing the nucleation region in Figures 1 and 2. Hereinafter, a method for manufacturing a GaN HEMT power semiconductor epitaxy wafer having a high-quality GaN channel region through growth temperature modulation according to embodiments of the present invention will be described in detail with reference to the drawings. In this process, the thicknesses of the layers or regions depicted in the drawings are exaggerated for the sake of clarity in the specification. Furthermore, the terms used below are selected for the convenience of explanation and should not be limited to their dictionary meanings but should be interpreted in a sense consistent with the technical concept of the present invention. Referring to FIG. 1, the method for manufacturing a GaN HEMT power semiconductor epitaxy wafer having a high-quality GaN channel region through growth temperature modulation according to the present embodiment sequentially grows an AlN nucleation region (120), a first GaN channel region (131), a second GaN channel region (132), a third GaN channel region (134), and an AlGaN barrier region (150). The AlN nucleation region (120) is formed on the growth substrate (110), and is typically formed inside an MOCVD chamber. The growth substrate (110) may be, for example, a silicon (Si)