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KR-102961319-B1 - METHOD OF GLASS DEPOSITION FOR SEMICONDUCTOR DEVICE FABRICATION

KR102961319B1KR 102961319 B1KR102961319 B1KR 102961319B1KR-102961319-B1

Abstract

A technique for plating a wafer with electrical glass during the manufacturing of semiconductor devices on a wafer. An electrically conductive network is formed within the wafer by doping the surface area of the wafer's isolation structure. The isolation structure isolates semiconductor devices laterally from each other within the wafer. After forming the electrically conductive network on the wafer, a glass deposition of each plating is formed on each of one or more plating areas of the wafer.

Inventors

  • 구, 싱총
  • 쪼우, 지팽
  • 허, 레이

Assignees

  • 리텔퓨즈 세미컨덕터 (우시) 씨오., 엘티디.

Dates

Publication Date
20260508
Application Date
20240124
Priority Date
20230130

Claims (20)

  1. A method for plating a wafer with glass while manufacturing a plurality of semiconductor devices on a wafer, The above method is, A step of forming an electrically conductive network on a wafer by doping a surface region of an isolation structure of a wafer including a substrate layer with a doping agent, and After forming the electrically conductive network on the wafer, forming plated glass on each of one or more plating regions of the wafer Includes, The above isolation structure is, The plurality of semiconductor devices within the wafer are laterally isolated from each other, and The above electrically conductive network is, Surrounding the plurality of semiconductor devices on the surface region, method.
  2. In paragraph 1, The above doping agent is, positive (P-type) or negative (N-type) polarity method.
  3. In paragraph 2, The above doping agent is, It is of the P type and contains boron, or The above doping agent is, N-type and containing phosphorus, method.
  4. In paragraph 1, The above doping agent is, It spreads laterally across the above surface area, and The above doping agent is, In terms of the thickness of the wafer, it is partially and vertically diffused through the isolation structure, and The above surface area is, Constituting the entire surface of the above isolation structure, The above electrically conductive network is, The above surface area including, method.
  5. In paragraph 1, At least one of the plurality of semiconductor devices above is, Includes thyristors, The above substrate layer is, Containing silicon, method.
  6. In paragraph 1, The above wafer is, (i) A lower base layer disposed below the above substrate layer, (ii) an upper base layer disposed on the substrate layer, and (iii) an upper layer disposed on the upper base layer above Includes, The upper layer mentioned above is, The area is smaller than that of the upper base layer, so that at least a portion of the upper base layer is exposed, and The above substrate layer is, Thicker than the thickness of each of the lower base layer, the upper base layer, and the upper layer, and Before plating with the above glass, (i) Each of the above substrate layer, the above upper base layer and the above isolation structure is, Partially exposed through each moat around each of the upper base layers of each of the plurality of semiconductor devices to be manufactured, and (ii) The above substrate layer is, Exposed only through each of the above moats, method.
  7. In paragraph 6, The lower base layer, the isolation structure, and the upper base layer are each positive type (P-type), and the substrate layer and the upper layer are each negative type (N-type), or or The lower base layer, the isolation structure, and the upper base layer are each of type N, and the substrate layer and the upper layer are each of type P. method.
  8. In paragraph 6, When forming the above electrically conductive network, the vertical remainder of the isolation structure in terms of the thickness of the lower base layer, the substrate layer, the upper base layer, the top layer, and the wafer is, Not doped with each of the above doping agents, method.
  9. In paragraph 6, Before forming the above electrically conductive network, The step of providing the substrate layer of the wafer, A step of forming the isolation structure by doping a first portion of the substrate layer, A step of forming the lower base layer of the wafer by doping the second portion of the substrate layer, A step of forming the upper base layer by doping a third portion of the substrate layer, and Step of forming the upper layer by doping only a portion of the upper base layer Includes more, The above third part is, For each moat, the island area defined by each of the above moats Includes, The above method is, Following the step of forming the above electrically conductive network, A step of forming each moat around the upper base layer of each of the plurality of semiconductor devices to be manufactured, and A step of dicing the wafer to separate the plurality of semiconductor devices from the wafer. Includes more, The lower base layer, the isolation structure, and the upper base layer are, Having a first polarity type, The above substrate layer and the above top layer are, having a second polarity type, method.
  10. In Paragraph 9, The lower base layer comprises a P lower base layer, the isolation structure comprises a P isolation structure, the substrate layer comprises an N- substrate layer, the upper base layer comprises a P upper base layer, and the upper layer comprises an N + upper layer, or or The lower base layer comprises an N lower base layer, the isolation structure comprises an N isolation structure, the substrate layer comprises a P- substrate layer, the upper base layer comprises a P upper base layer, and the upper layer comprises a P + upper layer. method.
  11. In paragraph 6, The upper layer mentioned above is, Includes a cathode, The above lower base layer is, Includes an anode, The above upper base layer is, including gates method.
  12. In paragraph 6, The above one or more plating areas are, For each of the above plurality of semiconductor devices, Each moat around the upper base layer of each of the above semiconductor devices, and Each of the one or more surface regions of the upper base layer of each of the above semiconductor devices Includes, Glass deposition is, Although not formed on the above electrically conductive network, At least a portion of the above glass deposition is, formed adjacent to the above electrically conductive network, method.
  13. In paragraph 1 The above doping agent is, N+ or P+ dopant, method.
  14. In paragraph 1, In terms of thickness, the degree of uniformity of the plating across the entire wafer is, Compared to a wafer that does not include the above electrically conductive network, If the above electrically conductive network exists, increasing, method.
  15. In Paragraph 14, The degree of uniformity mentioned above is, Increased by reducing the occurrence of the above plating, The above plating is, When measured relative to each other, the thickness varies, characterized by a relatively larger thickness at the boundary of the wafer and a relatively smaller thickness at the center of the semiconductor wafer. method.
  16. In paragraph 15, When the above electrically conductive network is absent, The above change in the thickness is, Attributable to the above wafer, The above wafer is, (i) relatively greater electrical conductivity at the boundary of the wafer due to the connection between the boundary of the wafer and one or more electrodes during the deposition of the glass, and (ii) Relatively low conductivity at the center of the wafer due to the isolation structure that reduces electrical conductivity at the center of the wafer compared to electrical conductivity at the boundary of the wafer Electrical conductivity changing, characterized by method.
  17. In a glass-plated wafer, The above wafer is, Isolation structure for isolating a plurality of semiconductor devices laterally within the wafer, An electrically conductive network formed by doping the surface area of the above-mentioned isolation structure with a doping agent, and Plated glass placed in each of one or more plating regions of the wafer Includes, The above electrically conductive network is, Surrounding the plurality of semiconductor devices on the surface region, Each of the above plurality of semiconductor devices is, Lower base layer, A substrate layer disposed on the lower base layer above, An upper base layer disposed on the above substrate layer, and An upper layer disposed on the upper base layer above. including, wafer.
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Description

Method of glass deposition for semiconductor device fabrication The embodiments presented in this disclosure relate to the field of semiconductor devices. More specifically, the embodiments disclosed herein relate to a technique for glass deposition for manufacturing semiconductor devices such as power switching devices. Semiconductor devices are widely used in the control of electric power, ranging from light dimmers and electric motor speed control to high-voltage direct current power transmission. For example, thyristors are used in AC power control applications. Because thyristors are characterized by their ability to rapidly switch from a non-conductive state to a conductive state, they can function as electric power switches. During operation, the thyristor is turned on and switches from a high-impedance state to a low-impedance state. This is accomplished by applying a voltage between the gate and the cathode and allowing current to flow from the gate to the cathode. FIG. 1 illustrates a cross-sectional view of a portion of a wafer during several stages of a manufacturing process including glass deposition, according to one embodiment presented in the present disclosure. FIG. 2 illustrates a cross-sectional view of a wafer portion during a subsequent stage of a manufacturing process including glass deposition, according to one embodiment presented in the present disclosure. FIG. 3 illustrates a plan view of a wafer during a subsequent stage of a manufacturing process including glass deposition, according to one embodiment presented in the present disclosure. FIG. 4 is a flowchart illustrating a manufacturing process including glass deposition according to one embodiment presented in the present disclosure. The embodiments presented in this disclosure provide a glass deposition technique for manufacturing semiconductor devices, such as power switching devices. One embodiment comprises forming an electrically conductive network on a wafer by doping a surface area of an isolation structure on the wafer. Then, a glass deposition is formed on one or more plating areas of the wafer. By doing so, at least in some cases, the degree of uniformity of the glass deposition across the wafer can be increased due to the presence of the electrically conductive network. For example, this can reduce the occurrence of glass deposition that is thicker at the boundaries of the wafer and thinner at the center of the wafer due to the presence of an isolation structure that has reduced electrical conductivity at the center compared to electrical conductivity at the boundary, for example, connected to an electrode during the glass deposition process. Advantageously, the semiconductor device can thereby be manufactured with a greater degree of quality, consistency, and/or efficiency. In this specification, embodiments are described by reference to specific examples of semiconductor devices for the purposes of illustration and explanation, but this is not intended to limit the scope of the disclosed embodiments. Specific examples constitute a thyristor, which is a known device based on four different semiconductor layers that are electrically arranged in series and are generally formed within a single-crystal substrate such as silicon. The thyristor comprises four layers composed of materials of an alternating positive (P) or negative (N) polarity type, with the layers disposed between the positive and negative electrodes. Those skilled in the art will recognize that other types of power switching devices and semiconductor devices can be manufactured more generally using the technology disclosed herein. FIG. 1 illustrates a cross-sectional view of a wafer portion during several stages of a manufacturing process including glass deposition according to one embodiment. This portion belongs to only one of several semiconductor devices to be manufactured on the wafer. The cross-sectional view corresponds to a vertical cross-section of the wafer, that is, a cross-section perpendicular to the surface of the wafer. As illustrated, in the first stage of the manufacturing process, the wafer (110) comprises a substrate layer (112), and the substrate layer (112) comprises silicon. Both the top surface and the bottom surface of the substrate layer (112) are doped using a doping agent (116) and a doping mask (114). In this specification, the top surface is also referred to as the upper surface or front surface, and the bottom surface is also referred to as the lower surface or rear surface. According to one embodiment, the doping mask (114) comprises an oxide. When the substrate layer (112) is an N - substrate layer, the doping agent (116) used is a P-doping agent. An example of a P-doping agent is boron, and an example of an N-doping agent is phosphorus. As used herein with respect to doping agents, superscript symbols or their omissions indicate relative doping concentrations, wherein a plus sign indicates a higher relative doping concent