KR-102961347-B1 - test SOCKET, INSERT CARRIER and test handler

Abstract

The present invention is a laser bonding device using a vision camera in which a guide probe is attached to a test socket and an interference escape groove into which the guide probe is inserted is formed on the lower surface of an insert carrier, so that the semiconductor device under test can be aligned quickly and precisely through the inclined guide portion and the vertical guide of the guide probe, thereby enabling the simultaneous mass testing of semiconductor devices with fine pitch, such as bare dies, even with existing test handler equipment.

Inventors

• 오창수

Assignees

• 주식회사 일레븐랩스

Dates

Publication Date

20260508

Application Date

20240820

Priority Date

20240719

Claims (14)

1. As a test socket for testing semiconductor devices under test, A socket substrate having upper conductive pads formed at each position corresponding to a terminal of a semiconductor device under test on an upper surface, and lower conductive pads electrically connected to the upper conductive pads on a lower surface; and It comprises conductive probes each attached to the upper conductive pads above, and At least one guide probe is attached and disposed in the outer region of the conductive probe of the socket substrate, which guides each of the four sides of the semiconductor device under test, A test socket characterized in that the challenge probe and the guide probe are attached to the socket substrate by a laser bonding device controlled by a vision camera.
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3. In paragraph 1, A test socket characterized in that the guide probe is attached to the socket substrate together with the conductive probe.
4. In paragraph 1, A test socket characterized by the above guide probe having an inclined guide portion that is inclined from the upper surface toward the front side of the conductive probe, and a straight vertical guide portion formed on the front side that is connected to the inclined guide portion and extends toward the lower surface.
5. In paragraph 4, A test socket characterized in that the inclined guide portion is one of a round shape, a tapered shape, or a shape combining a round shape and a tapered shape.
6. In paragraph 4, The above guide probe is a test socket characterized by having an alignment mark protruding from its upper surface, which is recognized by the vision camera.
7. In paragraph 6, The above-mentioned challenge probe has an alignment mark formed protruding from its upper surface that is recognized by the vision camera, and A test socket characterized in that the alignment mark of the guide probe and the alignment mark of the conductive probe have the same shape and size.
8. In paragraph 6, A test socket characterized by having an anti-light reflection slope formed around the alignment mark.
9. In paragraph 1, A test socket characterized in that the above guide probe is manufactured by a MEMS process.
10. In paragraph 1, A test socket characterized in that the guide probe has a longer vertical length than the conductive probe.
11. In paragraph 1, A test socket characterized in that the socket substrate is a pitch converter substrate in which the pitch between the lower conductive pads is greater than the pitch between the upper conductive pads.
12. An insert carrier that accommodates a semiconductor device to be tested and connects the semiconductor device to a test socket, The above test socket comprises: a socket substrate having upper conductive pads formed at positions corresponding to terminals of a semiconductor device to be tested on an upper surface, and lower conductive pads electrically connected to the upper conductive pads on a lower surface; conductive probes each attached to the upper conductive pads; and at least one guide probe attached to an outer region of the conductive probes of the socket substrate, each guiding four sides of the semiconductor device to be tested. The above-mentioned conductive probe and the above-mentioned guide probe are attached to the socket substrate by a laser bonding device controlled by a vision camera, and An insert carrier characterized by having an interference escape groove formed on the lower surface of the insert carrier facing the test socket, into which the guide probe is inserted at each position corresponding to the guide probe.
13. In Paragraph 12, An insert carrier characterized in that the interference escape groove has a width greater than 20㎛ than the thickness of the guide probe.
14. In a test handler comprising a loader section, a test section, and an unloader section, In the above test section, A test socket is disposed comprising: a socket substrate having upper conductive pads formed at positions corresponding to terminals of a semiconductor device to be tested on an upper surface, and lower conductive pads electrically connected to the upper conductive pads on a lower surface; conductive probes each attached to the upper conductive pads; and at least one guide probe each attached to an outer region of the conductive probes of the socket substrate to guide four sides of the semiconductor device to be tested. The above-mentioned conductive probe and the above-mentioned guide probe are attached to the socket substrate by a laser bonding device controlled by a vision camera, and A test tray is supplied in which an insert carrier housing the above-mentioned semiconductor device to be tested is installed, and The above-mentioned semiconductor device to be tested is connected to the above-mentioned test socket while mounted on the above-mentioned test tray and the test is performed, The test handler is characterized in that the insert carrier has an interference escape groove formed on the lower surface facing the test socket, at each position corresponding to the guide probe, into which the guide probe is inserted.

Description

test socket, insert carrier and test handler The present invention relates to a test socket, an insert carrier, and a test handler, and more specifically, to a test socket that electrically connects a fine-pitch semiconductor device to a test board, an insert carrier that is connected and aligned to the test socket, and a test handler using the test socket and the insert carrier. Semiconductor devices are formed by high-density integration of fine electronic circuits, and the normality of each electronic circuit can be tested during the manufacturing process. A semiconductor device to be tested (hereinafter referred to as the "semiconductor device under test") can be tested using a test socket that electrically connects the terminal of the semiconductor device under test to a signal pad of a test board that applies a test signal, and an insert carrier that contact-aligns the terminal of the semiconductor device under test to a conductive probe of the test socket. However, due to the advancement of semiconductor technology, the pitch between terminals of semiconductor devices is decreasing, and there is an increasing trend of utilizing individual dies formed by wafer dicing in a bare die state without packaging. A representative example of a device used in a bare die state is High Bandwidth Memory (HBM) semiconductors for artificial intelligence (AI). Since bare dies such as HBM semiconductors have a pitch between terminals of about 130㎛ to 100㎛, in order to test the semiconductor device under test in a bare die state, the pitch of the signal pads on the test board is also required to have a fine spacing (e.g., about 0.2mm or less) corresponding to this. As the pitch between terminals (pad or ball types, etc.) in semiconductor devices and dies decreases, it is becoming difficult to accommodate the pitch of conductive probes that contact the terminals of semiconductor devices in test sockets, and the ability to handle fine pitches of signal pads on test boards is reaching its limit. Therefore, most manufacturers find it difficult to test in a bare die state, so as shown in Fig. 1, they perform final testing in a wafer state using a probe card at a probe station, and then dice it into individual dies before delivering it to the customer. However, while defects may occur due to damage to individual dies caused by physical impact during the wafer dicing process, a problem arises where quality assurance is not properly provided because separate testing is not performed in the individual die state. Accordingly, a method has recently been attempted to test individual dies using probe cards by aligning them to the wafer chuck of a probe station using a vision camera. However, alignment using a vision camera requires a significant amount of time, and since the dies aligned to the wafer chuck require the insertion of alignment mechanisms, space is needed between the dies. Additionally, there are limitations on the probe card size corresponding to the wafer size, which makes mass testing impossible. In addition, the probe card method has the problem that high-speed testing is difficult because it is difficult to minimize the skew between signal lines and to configure transmission lines with low signal distortion, due to the need to configure multiple signal transmission lines within a relatively small area. In addition, for die alignment, the alignment mechanism must repeatedly contact the side or top surface of the die, and the bottom surface of the die must repeatedly contact the wafer chuck during die position correction, so the side of the die may be damaged or the terminals on the top surface (pad-shaped or ball-shaped) or the bottom surface may be contaminated or damaged. Furthermore, unlike large-area wafers, dies have small areas that are individually separated by dicing. Since the vacuum grooves of the wafer chuck adsorb and fix these small dies, the fixing force of the die secured to the wafer chuck becomes insufficient. In particular, when small foreign particles are placed on the wafer chuck, the vacuum pressure between the die and the wafer chuck is further reduced due to leakage. In this state, if force is applied to the die in the direction of scrubbing caused by the scrubbing that occurs when the conductive probes of the probe card contact the die terminals, there is a problem where the position of the die, which was difficult to align, becomes misaligned. In addition, instead of using probe stations, methods are also being attempted to test semiconductor devices in a bare die state by utilizing existing test handlers or burn-in facilities capable of mass testing. FIG. 2 relates to a conventional test socket device (10) for testing a semiconductor device to be tested, disclosed in Registered Patent Publication No. 10-213958. The conventional test socket device (10) comprises a pitch conversion substrate (11) including a plurality of conductive probes (13) arranged at intervals corresponding to the fine