KR-102961390-B1 - Array substrate, display panel and method of forming array substrate

KR102961390B1KR 102961390 B1KR102961390 B1KR 102961390B1KR-102961390-B1

Abstract

The present application relates to an array substrate, a display panel, and a method for forming an array substrate, wherein the array substrate comprises a base; a first type transistor, a second type transistor, and a capacitor installed to be stacked on one side of the base in the thickness direction, wherein the first type transistor comprises a first source-drain electrode, the second type transistor comprises a second source-drain electrode, and the capacitor comprises a device layer including a first electrode plate and a second electrode plate; wherein the first electrode plate is installed on the same layer as at least one of the first source-drain electrode and the second source-drain electrode, and the second electrode plate is installed on one side of the first type transistor and the second type transistor facing away from the base in the thickness direction. In the array substrate, display panel, and display device provided by the embodiment of the present application, the array substrate can increase the capacitance area by changing the position of the capacitor so that the electrode plate of the capacitor is extended outward or offset, which is advantageous for improving resolution and, furthermore, can reduce the risk of signal crosstalk through the installation position of the capacitor.

Inventors

왕, 제
먀오, 잔청
쑨, 단단
두, 저
바이, 칭
쑨, 야페이
루, 젠쥔
장, 펑
리, 쥔펑

Assignees

허페이 비젼녹스 테크놀로지 컴퍼니 리미티드
쿤산 고-비젼녹스 옵토-일렉트로닉스 씨오., 엘티디.

Dates

Publication Date: 20260508
Application Date: 20230113
Priority Date: 20220929

Claims (18)

As an array substrate, Base; and The above-mentioned base is installed to be stacked on one side in the thickness direction and includes a first type transistor, a second type transistor, and a capacitor, wherein the first type transistor includes a first source-drain electrode, the second type transistor includes a second source-drain electrode, and the capacitor includes a device layer comprising a first electrode plate and a second electrode plate; The first electrode plate is installed on the same layer as at least one of the first source-drain electrode and the second source-drain electrode, and the second electrode plate is installed on one side of the first type transistor and the second type transistor facing away from the base in the thickness direction. The above-mentioned device layer further includes a scan signal line and a data signal line, and the orthographic projection of the second electrode plate on the base covers the orthographic projection of at least a portion of at least one of the first electrode plate, the scan signal line, and the data signal line on the base.
In paragraph 1, An array substrate in which the first electrode plate, the first source-drain electrode, and the second source-drain electrode are all installed on the same layer.
In paragraph 1, The above-mentioned element layer further includes power wiring, and the power wiring and the second electrode plate are installed on the same layer of an array substrate.
In paragraph 1, The above-mentioned element layer further includes power wiring, and at least a portion of the power wiring is multiplexed to the second electrode plate, forming an array substrate.
In paragraph 1, The first type transistor further includes a first active region, and the second type transistor further includes a second active region; one side of the first active region and the second active region facing away from the base in the thickness direction is covered by a first insulating layer group, and a first via hole and a second via hole are installed in the first insulating layer group; the first source-drain electrode is connected to the first active region through the first via hole, and the second source-drain electrode is connected to the second active region through the second via hole; An array substrate in which the orthographic projection of the second electrode plate on the base and the orthographic projection of the first via hole and/or the second via hole on the base are installed staggeredly.
In paragraph 5, The array substrate wherein the first insulating layer group comprises a first sub-insulating layer installed to cover at least one of the first active region and the second active region, the first sub-insulating layer comprises insulating layer 1 and insulating layer 2 installed to be stacked in the thickness direction, the insulating layer 1 is located between the base and the insulating layer 2, and the thickness value range of the insulating layer 1 is 1200 Angstroms to 2000 Angstroms.
In paragraph 6, An array substrate in which the thickness of the above insulating layer 1 is in the range of 1400 Angstroms to 1800 Angstroms.
In paragraph 6, The insulating layer 1 comprises a silicon nitride layer and a silicon oxide layer installed to be stacked in the thickness direction, and the thickness of the silicon nitride layer is less than or equal to 1,000 Angstroms, in an array substrate.
In paragraph 6, An array substrate wherein the first insulating layer group further comprises a second sub-insulating layer, the second sub-insulating layer is installed on one side of the first sub-insulating layer facing away from the base in the thickness direction, and the thickness value range of the second sub-insulating layer is 3000 Angstroms to 8000 Angstroms.
In Paragraph 9, The above second sub-insulating layer is an array substrate comprising silicon oxide.
In paragraph 1, An array substrate wherein the first type transistor further comprises a first gate electrode, the second type transistor further comprises a second gate electrode, the first electrode plate is electrically connected to at least one of the first gate electrode and the second gate electrode, and the second electrode plate is electrically connected to at least one of the first source-drain electrode and the second source-drain electrode.
In Paragraph 11, The first gate electrode and the second gate electrode are an array substrate installed layer by layer.
In paragraph 1, The array substrate further comprises a second insulating layer, wherein the second insulating layer covers the array substrate including the first source-drain electrode and the second source-drain electrode.
In Paragraph 13, An array substrate in which the thickness of the second insulating layer is in the range of 1000 Angstroms to 1300 Angstroms.
In paragraph 1, An array substrate in which one of the first type transistor and the second type transistor is a low-temperature polycrystalline silicon thin film transistor and the other is an oxide thin film transistor.
As a display panel, A display panel comprising an array substrate according to any one of claims 1 to 15.
As a method for forming an array substrate, A step of providing a substrate base, wherein the substrate base comprises a base, a first active region and a second active region located on the base, a first gate electrode installed facing and insulatingly opposite the first active region, a second gate electrode installed facing and insulatingly opposite the second active region, and a first insulating layer group covering one side of the first active region and the second active region facing away from the base in the thickness direction of the substrate base; A step of patterning the first insulating layer group, wherein a first via hole and a second via hole are formed in the first insulating layer group, the first active region is partially exposed from the first via hole, and the second active region is partially exposed from the second via hole; A step of forming a first source-drain electrode connected to the first active region, a second source-drain electrode connected to the second active region, and a first electrode plate on one side of the first insulating layer group facing away from the base; A step of forming a second insulating layer on one side of the first source drain electrode, the second source drain electrode, and the first electrode plate facing away from the base; and The method includes the step of forming a second electrode plate on one side of the second insulating layer facing away from the base, wherein the second electrode plate and the first electrode plate together form a capacitor. A method for forming an array substrate in which the orthographic projection of the second electrode plate on the base covers the orthographic projection of at least a portion of at least one of the first electrode plate, scan signal line, and data signal line on the base.
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Description

Array substrate, display panel and method of forming array substrate Cross-reference of related applications This application claims priority to Chinese Patent Application No. 202211199942.8, filed on September 29, 2022, with the invention title “Method for forming array substrate, display panel and array substrate,” all contents of said application are incorporated herein by reference. The present application relates to the field of display technology, and in particular to an array substrate, a display panel, and a method for forming an array substrate. With the continuous improvement of high-resolution and highly innovative technologies in the display field and technological changes, user demand for the range of mobile terminal products is increasing. Low Temperature Polycrystalline Oxide (LTPO) technology integrates the low leakage current of indium gallium zinc oxide (IGZO) and the high mobility of low temperature polycrystalline silicon (LTPS) to enable the application of low-frequency displays to small and medium-sized panels, thereby significantly improving the range of products. Since the array substrate of LTPO technology extends into an LTPS array, the capacitor structure is located between the LTPS and IGZO devices, making it difficult to increase the area of the storage capacitance electrode plate, which is disadvantageous for improving resolution. Embodiments of the present application provide an array substrate, a display panel, and a method for forming the array substrate. By changing the position of the capacitor, the array substrate can extend or offset the electrode plate of the capacitor to increase the capacitance area, which is advantageous for improving resolution and, furthermore, can reduce the risk of signal crosstalk through the installation position of the capacitor. In one embodiment, an embodiment of the present application provides an array substrate, wherein the array substrate comprises a base; and a first type transistor, a second type transistor, and a capacitor installed to be stacked on one side of the base in the thickness direction, wherein the first type transistor comprises a first source-drain electrode, the second type transistor comprises a second source-drain electrode, and the capacitor comprises a device layer including a first electrode plate and a second electrode plate; wherein the first electrode plate is installed on the same layer as at least one of the first source-drain electrode and the second source-drain electrode, and the second electrode plate is installed on one side of the first type transistor and the second type transistor facing away from the base in the thickness direction. In another aspect, an embodiment of the present application provides a display panel, wherein the display panel comprises the array substrate. In another aspect, an embodiment of the present application provides a method for forming an array substrate, wherein the method is, A step of providing a substrate base, wherein the substrate base comprises a base, a first active region and a second active region located on the base, a first gate electrode installed facing and insulatingly from the first active region, a second gate electrode installed facing and insulatingly from the second active region, and a first insulating layer group covering one side of the first active region and the second active region facing away from the base in the thickness direction of the substrate base; A step of patterning a first insulating layer group, wherein a first via hole and a second via hole are formed in the first insulating layer group, a first active region is partially exposed from the first via hole, and a second active region is partially exposed from the second via hole; A step of forming a first source-drain electrode connected to a first active region, a second source-drain electrode connected to a second active region, and a first electrode plate on one side of a first insulating layer group facing away from the base; A step of forming a second insulating layer on one side of a first source drain electrode facing away from the base, a second source drain electrode, and a first electrode plate; and The method includes the step of forming a second electrode plate on one side of a second insulating layer facing away from the base, wherein the second electrode plate and the first electrode plate together form a capacitor. According to the array substrate, display panel, and method of forming the array substrate provided by an embodiment of the present application, the array substrate includes a base and a device layer, the device layer is installed on one side of the base in the thickness direction, the device layer includes a first type transistor, a second type transistor, and a capacitor, the first type transistor includes a first source-drain electrode, the second type transistor includes a second source-drain electrode, the first electrode plate of the capacitor is installed on