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KR-102961407-B1 - SEMICONDUCTOR PACKAGE

KR102961407B1KR 102961407 B1KR102961407 B1KR 102961407B1KR-102961407-B1

Abstract

One embodiment of the present invention comprises: a redistribution substrate having a first surface and a second surface opposite to the first surface, comprising a first insulating layer, a redistribution pattern disposed on the first insulating layer, and a redistribution via penetrating the first insulating layer and electrically connected to the redistribution pattern; a first semiconductor chip disposed on the first surface of the redistribution substrate and electrically connected to the redistribution pattern; a first sealing material disposed on the first surface of the redistribution substrate and sealing at least a portion of the first semiconductor chip; a passive element and a metal post disposed on the second surface of the redistribution substrate and electrically connected to the redistribution pattern; a second sealing material disposed on the second surface of the redistribution substrate and sealing at least a side of each of the passive element and the metal post; a second insulating layer disposed on the lower surface of the metal post and the lower surface of the second sealing material and having an opening that exposes at least a portion of the lower surface of the metal post; and a connection that fills the opening of the second insulating layer and directly contacts the exposed lower surface of the metal post. The semiconductor package includes bumps, and the metal posts have a height greater than the height of each of the rewiring pattern and the rewiring via.

Inventors

  • 김동규
  • 김민정
  • 석경림
  • 이석현

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260511
Application Date
20210322

Claims (10)

  1. A redistribution substrate having a first surface and a second surface opposite to the first surface, comprising a first insulating layer, a redistribution pattern disposed on the first insulating layer, and a redistribution via penetrating the first insulating layer and electrically connected to the redistribution pattern; A first semiconductor chip disposed on the first surface of the redistribution substrate and comprising a connection pad electrically connected to the redistribution pattern; A solder bump connecting the above connection pad and the above rewiring via; A first sealing material disposed on the first surface of the above-mentioned redistribution substrate and sealing at least a portion of the first semiconductor chip; A passive element and a metal post disposed on the second surface of the redistribution board and electrically connected to the redistribution pattern; A second sealant disposed on the second surface of the above-mentioned redistribution board and sealing at least the sides of each of the passive element and the metal post; A second insulating layer disposed on the lower surface of the metal post and the lower surface of the second sealant, having an opening that exposes at least a portion of the lower surface of the metal post; and It includes a connecting bump that fills the opening of the second insulating layer and directly contacts the lower surface of the exposed metal post, The metal post has a height greater than the height of each of the redistribution pattern and the redistribution via, and The above redistribution pattern includes a first redistribution pattern adjacent to the first surface and a second redistribution pattern adjacent to the second surface, and The above redistribution via includes a first redistribution via connecting the first redistribution pattern to the solder bump, a second redistribution via connecting the metal post to the second redistribution pattern, and a third redistribution via connecting the second redistribution pattern to the first redistribution pattern. A semiconductor package in which the width of the upper surface of the first redistribution via in contact with the solder bump and the width of the upper surface of the second redistribution via in contact with the second redistribution pattern are each larger than the width of the upper surface of the third redistribution via in contact with the first redistribution pattern.
  2. In Article 1, A semiconductor package in which the height of the metal post is in the range of 50㎛ to 100㎛.
  3. In Article 2, A semiconductor package in which the height of each of the above-mentioned redistribution pattern and the above-mentioned redistribution via is in the range of 5㎛ to 15㎛.
  4. In Article 1, The above-mentioned rewiring via is a semiconductor package having a tapered shape that narrows toward the first surface.
  5. In Article 1, A semiconductor package in which the lower surface of the metal post and the lower surface of the second sealant are in the same plane.
  6. In Article 5, A semiconductor package in which the height of the metal post is greater than the height of the passive element.
  7. In Article 1, The above connection bump is a semiconductor package comprising tin (Sn) or a metal alloy containing it.
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Description

Semiconductor Package The present invention relates to a semiconductor package. Semiconductor packages are mounted on a substrate (e.g., a main board) via various types of connection bumps. The connection reliability between the semiconductor package and the substrate is affected by the connection status between the connection bumps and the redistribution layer of the semiconductor package. To enhance the board-level reliability of the semiconductor package, an under-bump metal (UBM) structure is formed between the redistribution layer and the connection bumps (e.g., solder bumps). FIG. 1a is a cross-sectional view showing a semiconductor package according to one embodiment of the present invention. Figure 1b is a plan view of the semiconductor package of Figure 1a along the line I-I'. Figure 2 is a partial enlarged cross-sectional view showing region 'A' of Figure 1a. FIG. 3 is a partially enlarged cross-sectional view showing a semiconductor package according to one embodiment of the present invention. FIG. 4 is a partial enlarged cross-sectional view showing a semiconductor package according to one embodiment of the present invention. FIG. 5 is a partial enlarged cross-sectional view showing a semiconductor package according to one embodiment of the present invention. FIG. 6 is a cross-sectional view showing a semiconductor package according to one embodiment of the present invention. FIG. 7 is a cross-sectional view showing a semiconductor package according to one embodiment of the present invention. FIG. 8 is a cross-sectional view showing a semiconductor package according to one embodiment of the present invention. FIGS. 9a to 9e are cross-sectional views schematically illustrating the manufacturing process of the semiconductor package of FIG. 1a. Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings. FIG. 1a is a cross-sectional view showing a semiconductor package (100A) according to an embodiment of the present invention, FIG. 1b is a plan view showing the semiconductor package (100A) of FIG. 1a along the line I-I', and FIG. 2 is a partial enlarged cross-sectional view showing region 'A' of FIG. 1a. FIG. 1b is illustrated with some of the components shown in FIG. 1a omitted. Referring to FIGS. 1a to 2, a semiconductor package (100A) may include a rewiring substrate (110), at least one semiconductor chip (121, 122), a first sealing material (130), a metal post (140), a second sealing material (150), and a connecting bump (160). Additionally, the semiconductor package (100A) may further include at least one passive element (170) and/or a second insulating layer (151). The redistribution substrate (110) may have a first surface (S1) and a second surface (S2) opposite to the first surface (S1), and may include at least one first insulating layer (111), at least one redistribution pattern (112) disposed on the first insulating layer (111), and at least one redistribution via (113) penetrating the first insulating layer (111) and electrically connected to the redistribution pattern (112). The first insulating layer (111) may include an insulating resin. The insulating resin may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin in which an inorganic filler or/and glass fiber (Glass Fiber, Glass Cloth, Glass Fabric) is impregnated into these resins, for example, prepreg, ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine). The first insulating layer (111) may include a photosensitive resin such as PID (Photoimageable Dielectric) resin. In this case, the first insulating layer (111) may be formed thinner, and a fine redistribution pattern (112) and redistribution vias (113) may be formed. The first insulating layer (111) may include a plurality of first insulating layers (111) stacked in a vertical direction. For example, the first insulating layer (111) may include a first upper insulating layer (111a), a first intermediate insulating layer (111b), and a first lower insulating layer (111c). Depending on the process, the boundaries between insulating layers of different levels (111a, 111b, 111c) may be unclear. Also, for convenience of explanation, only three insulating layers (111a, 111b, 111c) are shown in the drawings, but embodiments of the present invention are not limited thereto. For example, in some embodiments, the redistribution substrate (110) may include two or more first intermediate insulating layers (111b) and a corresponding number of lower redistribution patterns (112b) and lower redistribution vias (113b). The redistribution pattern (112) may include a metallic material including, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The redistribution pattern (112) may include, for example, a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, and a signal (Signal