KR-102961408-B1 - SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME

KR102961408B1KR 102961408 B1KR102961408 B1KR 102961408B1KR-102961408-B1

Abstract

A semiconductor device according to an embodiment of the present invention comprises: a first structure including circuit elements on a substrate and a lower wiring structure electrically connected to the circuit elements; and a second structure on the first structure, wherein the second structure comprises: a conductive plate layer; gate electrodes spaced apart in a vertical direction on the conductive plate layer and extending in a first direction; separation regions penetrating the gate electrodes in the vertical direction and extending in the first direction; channel structures each including a channel layer penetrating the gate electrodes in the vertical direction and electrically connected to the conductive plate layer; through-contact plugs spaced apart from the gate electrodes and extending in the vertical direction and electrically connected to the lower wiring structure; first contacts each electrically connected to the channel layer; second contacts each electrically connected to the through-contact plugs; bit lines extending in the second direction and electrically connecting at least one of the first contacts and at least one of the second contacts arranged along a second direction perpendicular to the first direction. and may include dummy contacts connected to the bit lines and spaced apart from the through contact plugs.

Inventors

김준형
김강민
이창환
엄태민
이승민

Assignees

삼성전자주식회사

Dates

Publication Date: 20260508
Application Date: 20210514

Claims (10)

A first structure comprising a substrate, circuit elements on the substrate, and lower contacts and lower wirings electrically connected to the circuit elements; and It includes a second structure that overlaps the first structure in a vertical direction, and The above second structure is, Conductive plate layer; A stacked structure disposed on the conductive plate layer and having a memory cell region and a through-insulating region adjacent to the memory cell region, wherein the stacked structure comprises gate electrodes disposed in the memory cell region, sacrificial insulating layers disposed in the through-insulating region, and interlayer insulating layers disposed between the gate electrodes and between the sacrificial insulating layers; Separation regions penetrating the gate electrodes of the stacked structure in the vertical direction and extending in a first direction intersecting the vertical direction; Channel structures each comprising a channel layer that penetrates the gate electrodes of the stacked structure in the vertical direction and is electrically connected to the conductive plate layer in the memory cell region; In the above-mentioned through-insulation region, through-contact plugs that penetrate the sacrificial insulation layers of the laminated structure in the vertical direction and are connected to the lower wiring of the first structure; and It includes upper wiring structures on the above channel structures and the above through contact plugs, The above upper wiring structure is, Bit lines extending in the vertical direction and a second direction intersecting the first direction; First contacts disposed between the bit lines and the channel layers on the memory cell region above to electrically connect the bit lines and the channel layers; Second contacts disposed between the bit lines and the through contact plugs on the above-mentioned through-insulating region to electrically connect the bit lines and the through-contact plugs; and It includes dummy contacts disposed between the second contacts on the above-mentioned through-insulating region and connected to the bit lines, The above dummy contacts are a semiconductor device that overlaps the above sacrificial insulating layers and the above interlayer insulating layers in the vertical direction.
In Article 1, The above dummy contacts are a semiconductor device spaced apart from the above through-contact plugs.
In Article 1, The above second structure is, Upper insulating layers disposed on the above laminated structure, wherein the upper wiring structure is disposed thereon; First studs penetrating at least one of the upper insulating layers to electrically connect the channel layers and the first contacts to each other; and A semiconductor device further comprising second studs that penetrate at least one of the upper insulating layers and electrically connect the through contact plugs and the second contacts to each other.
In Paragraph 3, A semiconductor device in which the lower regions of the above dummy contacts are surrounded by an insulating material forming at least one of the above upper insulating layers.
In Paragraph 3, The above second structure is, A semiconductor device further comprising dummy studs connected to the lower regions of the above dummy contacts, disposed between the second studs, and spaced apart from the through contact plugs.
A first structure comprising a substrate, circuit elements on the substrate, and a lower wiring structure electrically connected to the circuit elements; and It includes a second structure that overlaps the first structure in a vertical direction, and The above second structure is, Conductive plate layer; Gate electrodes spaced apart in the vertical direction on the conductive plate layer and extending in a first direction intersecting the vertical direction; Separation regions penetrating the gate electrodes in the vertical direction and extending in the first direction; Channel structures each comprising a channel layer that penetrates the gate electrodes in the vertical direction and is electrically connected to the conductive plate layer; Through-contact plugs spaced apart from the gate electrodes in a second direction intersecting the first direction and the vertical direction, and extending in the vertical direction to be electrically connected to the lower wiring structure of the first structure; First contacts electrically connected to each of the channel layers on the above channel structures; Second contacts electrically connected to each of the through contact plugs on the above-mentioned through contact plugs; At least one of the first contacts arranged along the second direction and at least one of the second contacts are electrically connected, and bit lines extending in the second direction; and It includes dummy contacts spaced apart from the gate electrodes in the second direction, connected to the bit lines, and spaced apart from the through contact plugs. The upper surfaces of the first contacts, the upper surfaces of the second contacts, and the upper surfaces of the dummy contacts are in contact with the bit lines.
In Article 6, A semiconductor device in which the above dummy contacts are arranged so as not to overlap with the above through contact plugs in the vertical direction.
In Article 6, A semiconductor device in which the above dummy contacts are placed side by side with the above second contacts at the same height level as the above second contacts.
In Article 6, The second contacts are arranged at a lower arrangement density than the first contacts, and The above dummy contacts are a semiconductor device disposed between the second contacts in the first direction and between the second contacts in the second direction.
A semiconductor storage device comprising: a substrate, circuit elements on the substrate, and a lower wiring structure electrically connected to the circuit elements; a second structure superimposed in a vertical direction with respect to the first structure; and an input/output pad electrically connected to the circuit elements; and It includes a controller that is electrically connected to the semiconductor storage device through the input/output pad and controls the semiconductor storage device. The above second structure is, Conductive plate layer; Gate electrodes spaced apart in the vertical direction on the conductive plate layer and extending in a first direction intersecting the vertical direction; Separation regions penetrating the gate electrodes in the vertical direction and extending in the first direction; Channel structures each comprising a channel layer that penetrates the gate electrodes in the vertical direction and is electrically connected to the conductive plate layer; Through-contact plugs spaced apart from the gate electrodes in a second direction intersecting the first direction and the vertical direction, and extending in the vertical direction to be electrically connected to the lower wiring structure of the first structure; First contacts electrically connected to each of the channel layers on the above channel structures; Second contacts electrically connected to each of the through contact plugs on the above-mentioned through contact plugs; At least one of the first contacts arranged along the second direction and at least one of the second contacts are electrically connected, and bit lines extending in the second direction; and It includes dummy contacts spaced apart from the gate electrodes in the second direction, connected to the bit lines, and spaced apart from the through contact plugs. The upper surfaces of the first contacts, the upper surfaces of the second contacts, and the upper surfaces of the dummy contacts are data storage systems in contact with the bit lines.

Description

Semiconductor Devices and Data Storage Systems Including the Same The present invention relates to a semiconductor device and a data storage system including the same. In data storage systems that require data storage, there is a demand for semiconductor devices capable of storing high-capacity data. Accordingly, methods to increase the data storage capacity of semiconductor devices are being studied. For example, as one method to increase the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged in three dimensions instead of memory cells arranged in two dimensions is being proposed. FIG. 1 is a schematic plan view of a semiconductor device according to exemplary embodiments. FIG. 2 is a partially enlarged plan view illustrating a semiconductor device according to exemplary embodiments. FIGS. 3a and FIGS. 3b are schematic cross-sectional views of a semiconductor device according to exemplary embodiments. FIG. 4 is a perspective view illustrating some components of a semiconductor device according to exemplary embodiments. FIGS. 5a and FIGS. 5b are schematic cross-sectional views of a semiconductor device according to exemplary embodiments. FIG. 6 is a perspective view illustrating some components of a semiconductor device according to exemplary embodiments. FIGS. 7a and 7b are schematic cross-sectional views of a semiconductor device according to exemplary embodiments. FIG. 8 is a perspective view illustrating some components of a semiconductor device according to exemplary embodiments. FIGS. 9a and 9b are schematic cross-sectional views of a semiconductor device according to exemplary embodiments. FIGS. 10a and FIGS. 10b are schematic cross-sectional views of a semiconductor device according to exemplary embodiments. FIG. 11 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 12 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIGS. 13a to 18b are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. FIG. 19 is a schematic diagram illustrating a data storage system including a semiconductor device according to exemplary embodiments. FIG. 20 is a schematic perspective view of a data storage system including a semiconductor device according to an exemplary embodiment. FIG. 21 is a cross-sectional view schematically showing a semiconductor package according to an exemplary embodiment. Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings. FIG. 1 is a schematic plan view of a semiconductor device according to exemplary embodiments. FIG. 2 is a partially enlarged plan view illustrating a semiconductor device according to exemplary embodiments. FIG. 2 illustrates regions 'A' and 'B' of FIG. 1 in enlarged view side by side. FIGS. 3a and 3b are schematic cross-sectional views of a semiconductor device according to exemplary embodiments. FIG. 3a shows a cross-section along the cutting line I-I' crossing regions 'A' and 'B' of FIG. 2, and FIG. 3b shows cross-sections along the cutting lines II-II' and III-III' of FIG. 2. Referring to FIGS. 1 to 3c, a semiconductor device (100) may include a first structure (1) comprising a substrate (10) and a second structure (2) comprising a pattern structure (105). The second structure (2) may be disposed on the first structure (1). The first structure (1) is an area where peripheral circuit regions of the semiconductor device (100) are disposed, and a row decoder, page buffer, and other peripheral circuits may be disposed thereon. The second structure (2) is an area where memory cells of the semiconductor device (100) are disposed, and gate electrodes (130) and channel layers (140), etc. may be disposed thereon. The first structure (1) may include a substrate (10), element isolation layers (15s) defining an active region (15a) on the substrate (10), circuit elements (20) disposed on the substrate (10), a lower wiring structure (30) electrically connected to the circuit elements (20), and a lower capping insulating layer (40). The substrate (10) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The substrate (10) may be provided as a bulk wafer or an epitaxial layer. Device isolation layers (15s) are disposed within the substrate (10), and source/drain regions (22) containing impurities may be disposed in a part of the active region (15a). The circuit elements (20) may each include a transistor comprising a source/drain region (22), a circuit gate dielectric layer (24), and a circuit gate electrode (26). The source/drain regions (22) may be placed on both sides of the circuit gate electrode (25) in the active region (15a). The circuit gate dielectric layer (24) may be placed between t