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KR-102961419-B1 - A MEMORY DEVICE and ELECTRONIC DEVICE INCLUDING A RECEIVING CIRCUIT

KR102961419B1KR 102961419 B1KR102961419 B1KR 102961419B1KR-102961419-B1

Abstract

A memory device including a receiving circuit is provided. The receiving circuit includes a first pass that receives a receiving signal and directly connects it to a current clock signal to output a first correction signal; a second pass that holds or tracks the receiving signal according to the clock signal and outputs a second correction signal held according to a previous clock signal; an adder that sums the first correction signal and the second correction signal to output a summed receiving signal; and a decision feedback equalizer that compares the summed receiving signal with a reference signal according to the current clock signal, determines the result, and outputs it.

Inventors

  • 권대현
  • 김민형
  • 김왕수

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260511
Application Date
20220203
Priority Date
20211108

Claims (10)

  1. In a memory device including a receiving circuit, The above receiving circuit is A first pass that receives a reception signal from a second clock signal and directly connects it to output a first correction signal; A second pass that holds a second correction signal in a first clock signal prior to the second clock signal, and outputs the held second correction signal in the second clock signal; An adder that sums the first correction signal and the second correction signal to output a summed reception signal; and It includes a decision feedback equalizer that compares and determines the summed received signal with a reference signal according to the second clock signal and outputs the result. The first correction signal is generated from a received signal received by the second clock signal, and the second correction signal is generated from a received signal received by the first clock signal. A memory device in which the first clock signal and the second clock signal are signals having the same period and the same duty ratio but having a phase difference of 90 degrees from each other.
  2. In paragraph 1, the second pass is A CML (current Mode Level) latch that holds the second modification signal received from the first clock signal and outputs the second modification signal from the second clock signal; and A memory device comprising a tap that outputs by reflecting a tap coefficient in the output signal to the second modification signal output from the above CML latch.
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  4. In paragraph 2, the memory device further comprises a buffer that delays the received signal and outputs it to the CML latch.
  5. In paragraph 1, the above adder A memory device that subtracts the second correction signal from the first correction signal and outputs the summed reception signal.
  6. A step of receiving a first reception signal through a channel; A step of holding a first received signal according to a first clock signal; A step of receiving a second receiving signal according to a second clock signal; A step of generating a summed-up received signal by subtracting the held first received signal from the second received signal; and The method includes a step of comparing the summed received signal with a reference signal and outputting the comparison result determined according to the second clock signal as the final received signal. A method for processing a received signal of an electronic device, wherein the first clock signal and the second clock signal have the same period and the same duty ratio but have a phase difference of 90 degrees from each other.
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  8. A method for processing a received signal of an electronic device, wherein, in claim 6, the step of outputting the final received signal is performed in a decision feedback equalizer that operates based on the second clock signal.
  9. In paragraph 6, the holding step above A method for processing a received signal of an electronic device, which is performed in a CML (current mode level) latch that holds the first received signal during the interval in which the first clock signal is enabled.
  10. In paragraph 9, the summed received signal is A method for processing a received signal of an electronic device, wherein the first tap coefficient set in the first received signal held above is reflected in the second received signal and the signal is generated by subtracting it.

Description

A memory device and an electronic device including a receiving circuit, and a method for processing the received signal. The present invention relates to a receiving circuit, in particular to an interface of an electronic device. As electronic devices become faster and less energized, the memory devices embedded within them also require fast read/write operations and low operating voltages. Random Access Memory (RAM) can be volatile or non-volatile. Volatile RAM loses information stored in it whenever power is removed, whereas non-volatile RAM can retain its contents even when power is removed from the memory. DRAM (Dynamic Random Access Memory) data transmission methods include the multi-drop channel method, which connects multiple chips simultaneously to a single signal line to increase transmission data capacity, and the single-ended method, which reduces the number of signal lines and pins. The multi-drop channel method is a configuration in which multiple DRAM chips are connected to a single signal line. Parasitic resistance, parasitic inductance, and parasitic capacitance exist at the input pins of the DRAM chips. Due to these parasitic components, signal attenuation occurs in the multidrop method, reducing the channel frequency band. This acts as Inter-Symbol Interference (ISI) in high-frequency signal transmission, which can reduce the voltage and time margins of the transmitted signal. Generally, equalizers are widely used to eliminate ISI. FIG. 1 is a block diagram showing a transmission circuit and a reception circuit according to some embodiments. Figure 2 is a conceptual diagram illustrating an input signal to a lossy channel and an output signal from a non-ideal channel, showing the effects of inter-symbol interference. FIG. 3 is a block diagram showing a receiving equalizer according to some embodiments. FIG. 4 is a drawing showing an embodiment of the receiving lighter illustrated in FIG. 3. FIG. 5 is an operation timing diagram of a receiving equalizer according to some embodiments. FIGS. 6 and FIGS. 7 are block diagrams showing a memory system according to some embodiments of the present invention. FIG. 8 is a block diagram showing electronic devices equipped with receiving circuits according to some embodiments. Hereinafter, with reference to FIGS. 1 to 8, a memory device according to some embodiments of the present invention will be described. Terms such as "unit" and "module" used below, or functional blocks illustrated in the drawings, may be implemented in the form of software configurations, hardware configurations, or combinations thereof. In order to clearly explain the technical concept of the present invention, detailed descriptions of redundant components are omitted below. FIG. 1 is a block diagram showing a first transmission circuit and a first reception circuit according to some embodiments, and FIG. 2 is a conceptual diagram showing an input signal to a lossy channel and an output signal from a non-ideal channel, showing the effects of inter-symbol interference. For the sake of brevity in the drawings, components unnecessary for explaining the technical concept of the present invention are omitted. Hereinafter, for convenience of explanation, terms such as "signal," "data," "symbol," and "bit" are used to denote signals generated, transmitted, or received between components. These terms are intended to concisely describe embodiments of the present invention, and each term will be understood in organic combination with the function of each component. In addition, to clearly explain the technical concept of the present invention, the receiving equalizer (100) is assumed to be a decision feedback equalizer (DFE). However, the scope of the present invention is not limited thereto, and the transmitting equalizer (100) can be implemented as one of various types of signal compensation circuits. Referring to FIG. 1, the transmission circuit (1) may include a transmission equalizer (10) and a transmission driver (TX, 11). The transmission equalizer (10) receives input data (DT_in) and can output an output signal (S T ) based on the received input data (DT_in). The receiving circuit (2) may include a receiving driver (RX, 30) and a receiving equalizer (100). The receiving driver (30) may receive an output signal (S T ) transmitted from the transmitting circuit (1) through the channel (20) and output a receiving signal (S R ). In an exemplary embodiment, as the output signal (S T ) passes through the channel (20), it may be distorted due to the response characteristics or noise of the channel (20). That is, the receiving driver (30) may output a receiving signal (S R ) that is distorted by the channel (20) and noise. In other words, the receiving signal (S R ) may be a signal in which the response characteristics and noise of the channel (20) are reflected in the output signal (S T ). In an exemplary embodiment, when the transmission equalizer (10) operates ideally so that inter-symbo