KR-102961466-B1 - Erase and reset method for 3D NAND flash memory

Abstract

A method for erasing stored data of a three-dimensional (3D) memory device is disclosed. The 3D memory device includes a plurality of memory blocks, and each memory block has a plurality of memory strings having memory cells stacked vertically. Each memory cell is addressable through a word line and a bit line. The stored data of a selected memory block can be erased by applying an erase voltage to an array common source and applying a first voltage to the word line of the selected memory block. The word line of a non-selected memory block is in a floating state, that is, a state without external bias, during the erase operation. After the erase operation, a second voltage is applied to the word line of the entire memory plane to reset the memory cell and improve data retention.

Inventors

• 탕 퀴앙
• 왕 리 웨이

Assignees

• 양쯔 메모리 테크놀로지스 씨오., 엘티디.

Dates

Publication Date

20260508

Application Date

20201204

Claims (20)

1. A method for operating a three-dimensional (3D) memory device including a memory block, Each memory block includes a memory string having vertically stacked memory cells, and each vertically stacked memory cell is addressable through word lines and bit lines, and The above method is, A step of applying a first voltage to a word line of a selected memory block at a first time point to perform an erase operation on the selected memory block, and A step of prohibiting the erasure operation for the unselected memory block by increasing the voltage of the word line of the unselected memory block to a second voltage greater than the first voltage from a second time point earlier than the first time point to a third time point later than the first time point, and After performing the above erase operation, the method comprises the step of applying a reset voltage to the word line of the unselected memory block to reset the unselected memory block. method.
2. In paragraph 1, The step of performing the erase operation on the selected memory block is as follows: The step of applying an erase voltage to the array common source of the selected memory block, and The first voltage is smaller than the erase voltage to erase the selected memory block, method.
3. In paragraph 1, The step of applying the first voltage includes applying a voltage in the range of 0V to 1V. method.
4. In paragraph 1, The step of applying the first voltage includes applying a voltage of 0V. method.
5. In paragraph 2, The step of applying the above-mentioned erasure voltage includes applying a voltage in the range of 15V to 25V, method.
6. In paragraph 2, The method further includes the step of resetting the selected memory block after performing the above erase operation, wherein the resetting step includes applying the reset voltage to the word line of the selected memory block. method.
7. In paragraph 6, A method further comprising the step of applying a voltage of 0V to the array common source of the selected memory block after performing the above erase operation. method.
8. In paragraph 2, Before performing the above erase operation, a step of applying a voltage of 0V to the word line of the selected memory block, and Subsequently, the method further comprises the step of removing the 0V voltage from the word line of the selected memory block so that the word line of the selected memory block becomes floating without external bias. method.
9. In paragraph 1, The step of applying the reset voltage includes applying a voltage in the range of 1.5V to 3.5V. method.
10. In paragraph 1, The step of prohibiting the erase operation for the above-mentioned unselected memory block includes making the word line of the above-mentioned unselected memory block a floating state without external voltage. method.
11. In paragraph 1, The step of prohibiting the erasure operation for the above-mentioned non-selected memory block further includes making the array common source of the above-mentioned non-selected memory block a floating state. method.
12. As a three-dimensional (3D) memory device, Including peripheral circuits, The above peripheral circuit is A first voltage is applied to the word line of a selected memory block at a first time point to perform an erase operation on the selected memory block, and The voltage of the word line of the unselected memory block is increased to a second voltage greater than the first voltage from a second time point earlier than the first time point to a third time point later than the first time point, thereby prohibiting the erase operation for the unselected memory block, After performing the above erase operation, configured to apply a reset voltage to the word line of the unselected memory block to reset the unselected memory block, 3D memory device.
13. In Paragraph 12, During the above erasure operation, the peripheral circuit, An erase voltage is applied to the array common source of the selected memory block, and The first voltage is smaller than the erase voltage to erase the selected memory block, 3D memory device.
14. In Paragraph 12, The first voltage above includes a voltage in the range of 0V to 1V, 3D memory device.
15. In Paragraph 12, The above first voltage is a voltage of 0V, 3D memory device.
16. In Paragraph 13, The above-mentioned erasure voltage includes a voltage in the range of 15V to 25V, 3D memory device.
17. In Paragraph 12, The above peripheral circuit is, Further configured to reset the selected memory block after performing the above erase operation, and the reset voltage is applied to the word line of the selected memory block, 3D memory device.
18. In Paragraph 17, The above reset voltage includes a voltage in the range of 1.5V to 3.5V, 3D memory device.
19. In Paragraph 17, The above peripheral circuit is, Before performing the above erase operation, a voltage of 0V is applied to the word line of the selected memory block, and Subsequently, further configured to remove the 0V voltage from the word line of the selected memory block so that the word line of the selected memory block becomes floating without external bias, 3D memory device.
20. In Paragraph 19, While prohibiting the erase operation for the aforementioned unselected memory block, the peripheral circuit, Making the word line of the above unselected memory block floating without external voltage, and Further configured to make the array common source of the above-mentioned unselected memory block a floating state, 3D memory device.

Description

Erase and reset method for 3D NAND flash memory The present disclosure generally relates to the field of semiconductor technology, and more specifically to a method for erasing and resetting a three-dimensional (3D) memory. As memory devices are reduced to smaller die sizes to lower manufacturing costs and increase storage density, the scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations of planar memory cells. In 3D NAND flash memory, storage density per unit area can be significantly increased by vertically stacking multiple layers of memory cells. Memory cells within a memory page that share the same word line can be programmed and read simultaneously, while memory cells in an entire memory block that shares a common source line are erased simultaneously. Memory cells performing the erase operation are typically biased with high voltage to remove stored data (or stored charge carriers), which can cause defects in the memory film of the memory cell and induce mobile charges. Therefore, there is a need for a method to erase and reset memory blocks to improve the data retention of 3D NAND memory. An example of a method for erasing and resetting a three-dimensional (3D) memory device is described in the present disclosure. One aspect of the present invention provides a method for operating a three-dimensional (3D) memory device having memory blocks, wherein each memory block comprises a memory string having vertically stacked memory cells, and each vertically stacked memory cell is addressable through word lines and bit lines. The method comprises the following steps: performing an erase operation on a selected memory block; prohibiting an erase operation on a non-selected memory block; and, after performing the erase operation, applying a reset voltage to the word lines of the non-selected memory block to reset the non-selected memory block. In some embodiments, the step of performing an erase operation on a selected memory block includes the step of applying an erase voltage to an array common source of the selected memory block and the step of applying a first voltage on a word line of the selected memory block, wherein the first voltage is smaller than the erase voltage to erase the selected memory block. In some embodiments, the first voltage includes a voltage in the range of about 0 V to about 1 V. In some embodiments, the first voltage includes a voltage of about 0 V. In some embodiments, the erase voltage includes a voltage in the range of about 15V to about 25V. In some embodiments, the method of operating a 3D memory device further includes the step of resetting a selected memory block after performing an erase operation, wherein the resetting step includes the step of applying a reset voltage to a word line of the selected memory block. In some embodiments, the method of operating a three-dimensional memory device further includes the step of applying a voltage of about 0V to an array common source of a selected memory block after performing an erase operation. In some embodiments, the method of operating a 3D memory device further includes the step of applying a voltage of about 0V to a word line of a selected memory block before performing an erase operation, and subsequently removing a voltage of about 0V from a word line of a selected memory block so that the word line of the selected memory block becomes floating without external bias. In some embodiments, the reset voltage includes a voltage in the range of about 1.5V to about 3.5V. In some embodiments, the step of prohibiting an erase operation for an unselected memory block includes making the word line of the unselected memory block floating without an external voltage. In some embodiments, the step of prohibiting erase operations for unselected memory blocks also includes making the array common source of unselected memory blocks floating. Another aspect of the present invention provides a three-dimensional (3D) memory device structure. The 3D memory device includes a peripheral circuit configured to perform an erase operation on a selected memory block, prohibit an erase operation on a non-selected memory block, and apply a reset voltage to the word line of the non-selected memory block to reset the non-selected memory block after the erase operation. In some embodiments, during an erase operation, the peripheral circuit is configured to apply an erase voltage to the array common source of the selected memory block and to apply a first voltage on the word line of the selected memory block, wherein the first voltage is smaller than the erase voltage to erase the selected memory block. In some embodiments, the peripheral circuit is additionally configured to reset the selected memory block after performing an erase operation, and the reset voltage is applied to the word line of the selec