KR-102961524-B1 - RADIO-FREQUENCY POWER DETECTOR WITH NON-LINEARITY CANCELLATION

Abstract

The wireless circuit may include a radio frequency amplifier and a power detection circuit coupled to the output of the radio frequency amplifier. The power detection circuit may include an input transistor, a biasing circuit configured to output a bias voltage for the input transistor and to track temperature and voltage changes, and a nonlinearity suppression component configured to generate a current that at least partially suppresses the nonlinear current associated with the input transistor. The input transistor may be an n-type transistor, and the nonlinearity suppression component may be a p-type metal oxide semiconductor capacitor. The biasing circuit may include n-type and p-type diode-connected bias transistors.

Inventors

• 아보우지에드, 모하메드
• 코미자니, 아바스

Assignees

• 애플 인크.

Dates

Publication Date

20260508

Application Date

20240308

Priority Date

20230309

Claims (20)

1. As a wireless circuit part, radio frequency amplifier; and It includes a power detection circuit coupled to the output of the above-mentioned radio frequency amplifier, wherein the power detection circuit, An input transistor having a gate terminal coupled to the output of the above radio frequency amplifier, A nonlinearity elimination component having a first terminal coupled to the gate terminal of the input transistor, and A wireless circuit comprising a first bias transistor having a first source-drain terminal coupled to a second terminal of the above-mentioned nonlinearity cancellation component and a second source-drain terminal coupled to the gate terminal of the above-mentioned input transistor.
2. In claim 1, the wireless circuit part wherein the nonlinearity cancellation component comprises a metal oxide semiconductor (MOS) capacitor.
3. A wireless circuit portion according to claim 1, wherein the input transistor comprises an n-type metal oxide semiconductor transistor and the nonlinearity cancellation component comprises a p-type metal oxide semiconductor capacitor.
4. A wireless circuit portion according to claim 1, wherein the nonlinearity cancellation component comprises a metal oxide semiconductor (MOS) capacitor, and the second terminal of the nonlinearity cancellation component is coupled to a shunt capacitor.
5. A wireless circuit portion according to claim 1, wherein the nonlinearity elimination component comprises a metal oxide semiconductor (MOS) capacitor, the first terminal of the nonlinearity elimination component comprises the gate terminal of the MOS capacitor, and the second terminal of the nonlinearity elimination component comprises the body terminal of the MOS capacitor and is coupled to a shunt capacitor.
6. In paragraph 5, the power detection circuit is, An additional input transistor having a gate terminal coupled to the output of the radio frequency amplifier and a source-drain terminal shorted to the input transistor; and A wireless circuit part further comprising an additional MOS capacitor having a gate terminal coupled to the gate terminal of the additional input transistor and a body terminal short-circuited to the body terminal of the MOS capacitor.
7. In paragraph 6, The above first bias transistor is a wireless circuit having a gate terminal shorted to its second source-drain terminal.
8. In paragraph 7, the power detection circuit is, A wireless circuit part further comprising a source terminal coupled to a ground line, a drain terminal coupled to the gate terminal of the first bias transistor, and a second bias transistor having a gate terminal coupled to the gate terminal of the input transistor.
9. In paragraph 8, the power detection circuit is, A first cascode transistor coupled in series with the above input transistor; A second cascode transistor; and A wireless circuit part further comprising a third bias transistor having a source terminal coupled to the drain terminal of the second bias transistor, a drain terminal coupled to a second current source, and a gate terminal short-circuited to the drain terminal thereof, wherein the third bias transistor is configured to provide a cascode bias voltage to the gate terminals of the first and second cascode transistors.
10. In Paragraph 9, The above MOS capacitor includes a p-type MOS capacitor, and The first bias transistor above includes a p-type bias transistor, and The above second and third bias transistors include n-type bias transistors, in a wireless circuit section.
11. As a power detection circuit, A first input transistor having a gate terminal configured to receive a radio frequency signal; A second input transistor having a gate terminal directly coupled to the first input transistor and configured to receive the radio frequency signal; A biasing circuit configured to provide bias voltages to the gate terminals of the first and second input transistors; A first nonlinearity elimination component having a first terminal coupled to the gate terminal of the first input transistor and a second terminal; and A power detection circuit comprising a second nonlinearity elimination component having a first terminal coupled to the gate terminal of the second input transistor and a second terminal short-circuited to the second terminal of the first nonlinearity elimination component.
12. delete
13. In Paragraph 11, The first nonlinearity cancellation component includes a first metal oxide semiconductor (MOS) capacitor, and The above-mentioned second nonlinearity cancellation component is a power detection circuit comprising a second metal oxide semiconductor (MOS) capacitor.
14. In Paragraph 13, The biasing circuit further includes a cascode transistor coupled to the first and second input transistors, and the biasing circuit, A first diode-connected bias transistor having a terminal coupled to the first and second nonlinearity cancellation components and coupled to a first current source, A second diode-connected bias transistor coupled to the first diode-connected bias transistor and configured to output the bias voltages, and A power detection circuit comprising a third diode-connected bias transistor coupled to the second diode-connected bias transistor, having a terminal coupled to a second current source, and configured to output a cascode bias voltage to the cascode transistor.
15. A power detection circuit according to claim 13, wherein the gate terminal of the first input transistor is coupled to a radio frequency amplifier through a first capacitor, and the gate terminal of the second input transistor is coupled to the radio frequency amplifier through a second capacitor.
16. As a circuit part, An input transistor configured to receive a radio frequency signal from a radio frequency amplifier; A biasing circuit configured to output a bias voltage for the input transistor and configured to track temperature and voltage changes; and It includes a nonlinearity nullification component configured to generate a current that at least partially nullifies the nonlinear current associated with the input transistor, and The above biasing circuit comprises a circuit part having a source terminal coupled to the main body terminal of the nonlinearity elimination component and a first current source, a gate terminal, and a drain terminal shorted to the gate terminal.
17. In claim 16, the above-mentioned nonlinearity cancellation component is a circuit part comprising a metal oxide semiconductor (MOS) capacitor.
18. In Paragraph 16, An additional input transistor configured to receive the radio frequency signal from the radio frequency amplifier; and A circuit part further comprising an additional nonlinearity elimination component configured to generate a current that at least partially eliminates the nonlinear current associated with the additional input transistor.
19. In Paragraph 18, The above input transistor and the above additional input transistor include n-type input transistors, and The above nonlinearity cancellation component includes a first p-type metal oxide semiconductor (MOS) capacitor having a gate terminal coupled to the gate terminal of the input transistor and a body terminal coupled to the biasing circuit, and The above additional nonlinearity elimination component comprises a circuit part including a second p-type metal oxide semiconductor (MOS) capacitor having a gate terminal coupled to the gate terminal of the additional input transistor and a body terminal coupled to the biasing circuit.
20. In claim 19, the above bias transistor comprises a p-type bias transistor, in a circuit portion.

Description

Radio-Frequency Power Detector with Non-Linearity Cancellation This application claims priority to U.S. Patent Application No. 18/181,466 filed March 9, 2023, the entirety of which is incorporated herein by reference. Technology field The present disclosure generally relates to electronic devices, and more specifically to electronic devices having a wireless communication circuit. Electronic devices may be provided with wireless communication capabilities. An electronic device having wireless communication capabilities has a wireless communication circuit having one or more antennas. The wireless transceiver circuit of the wireless communication circuit transmits and receives radio frequency signals using the antennas. Radio frequency signals transmitted by an antenna can be fed through a power amplifier configured to amplify low-power analog signals into high-power signals more suitable for transmission over long distances. Radio frequency signals received by the antenna can be fed through a low-noise amplifier configured to amplify low-power analog signals into higher-power signals for ease of processing at the receiver. Designing a satisfactory radio frequency amplifier for electronic devices can be difficult. The electronic device may include a wireless communication circuit. The wireless communication circuit may include one or more processors or signal processing blocks for generating baseband signals, a transceiver for upconverting (modulating) baseband signals to radio frequencies and downconverting (demodulating) radio frequency signals to baseband signals, a radio frequency power amplifier for amplifying radio frequency signals before transmission at one or more antennas, and a radio frequency low-noise amplifier for amplifying radio frequency signals received at one or more antennas within the electronic device. An embodiment of the present disclosure provides a radio circuit comprising a radio frequency amplifier and a power detection circuit coupled to the output of the radio frequency amplifier. The power detection circuit may include an input transistor having a gate terminal coupled to the output of the radio frequency amplifier, and a nonlinearity cancellation component coupled to the gate terminal of the input transistor. The nonlinearity cancellation component may be a metal oxide semiconductor (MOS) capacitor. The power detection circuit may further include an additional input transistor having a gate terminal coupled to the output of the radio frequency amplifier, and an additional MOS capacitor having a gate terminal coupled to the gate terminal of the additional input transistor and a body terminal coupled to a shunt capacitor. The power detection circuit may further include a first bias transistor having a source terminal coupled to the body terminal of a MOS capacitor and coupled to a first current source, a gate terminal, and a drain terminal shorted to its gate terminal. The power detection circuit may further include a second bias transistor having a source terminal coupled to a ground line, a drain terminal coupled to the drain terminal of the first bias transistor, and a gate terminal shorted to its drain terminal, wherein the second bias transistor is configured to provide a bias voltage to the gate terminal of the input transistor. The power detection circuit may further include a first cascode transistor coupled in series with the input transistor, a second cascode transistor, and a third bias transistor having a source terminal coupled to the drain terminal of the second bias transistor, a drain terminal coupled to a second current source, and a gate terminal shorted to its drain terminal, wherein the third bias transistor is configured to provide a cascode bias voltage to the gate terminals of the first and second cascode transistors. An aspect of the present disclosure provides a power detection circuit comprising a first input transistor configured to receive a radio frequency signal, a second input transistor configured to receive a radio frequency signal, a biasing circuit configured to provide bias voltages for the first and second input transistors, and a first nonlinearity elimination component coupled between the first input transistor and the biasing circuit. The power detection circuit may further comprise a second nonlinearity elimination component coupled between the second input transistor and the biasing circuit. While the first nonlinearity elimination component may be a first metal oxide semiconductor (MOS) capacitor having a gate terminal coupled to the gate terminal of the first input transistor and a body terminal coupled to the biasing circuit, the second nonlinearity elimination component may be a second metal oxide semiconductor (MOS) capacitor having a gate terminal coupled to the gate terminal of the second input transistor and a body terminal coupled to the biasing circuit. The bias circuit may include a first diode-connected bias transistor having