KR-102961569-B1 - Semiconductor package

KR102961569B1KR 102961569 B1KR102961569 B1KR 102961569B1KR-102961569-B1

Abstract

The present invention relates to a semiconductor package, and more specifically, may include a package substrate, an interposer substrate disposed on the package substrate, the interposer substrate comprising a first redistribution substrate, a second redistribution substrate on the lower surface of the first redistribution substrate, and an interposer molding film interposed between the first redistribution substrate and the second redistribution substrate, a connection substrate disposed on the interposer substrate, the connection substrate having a connection hole penetrating the interior thereof, a first semiconductor chip mounted on the interposer substrate, the first semiconductor chip disposed within the connection hole, a second semiconductor chip mounted on the interposer substrate, the second semiconductor chip being horizontally spaced apart from the first semiconductor chip, the second semiconductor chip disposed within the connection hole, and a connection semiconductor chip mounted on the lower surface of the first redistribution substrate and disposed within the interposer molding film.

Inventors

강명삼
고영찬
김정석
문경돈

Assignees

삼성전자주식회사

Dates

Publication Date: 20260507
Application Date: 20210503

Claims (10)

Package substrate; An interposer substrate disposed on the above-mentioned package substrate, wherein the interposer substrate comprises a first redistribution substrate, a second redistribution substrate on the lower surface of the first redistribution substrate, and an interposer molding film interposed between the first redistribution substrate and the second redistribution substrate; A connecting board disposed on the upper surface of the first redistribution board, wherein the connecting board has a connecting hole penetrating its interior; A first semiconductor chip mounted on the upper surface of the first rewiring board, wherein the first semiconductor chip is disposed within the connection hole; A second semiconductor chip mounted on the upper surface of the first rewiring board, wherein the second semiconductor chip is horizontally spaced apart from the first semiconductor chip, and the second semiconductor chip is disposed within the connection hole; and It includes a connection semiconductor chip mounted on the lower surface of the first redistribution board and disposed within the interposer molding film, The above interposer molding film is a semiconductor package that covers the upper surface of the connected semiconductor chip and the lower surface of the connected semiconductor chip.
In Article 1, A semiconductor package in which the upper surface of the first semiconductor chip is located at a higher level than the upper surface of the connection substrate.
In Article 1, A semiconductor package disposed on the interposer substrate and further comprising a sidewall of the first semiconductor chip, a sidewall of the second semiconductor chip, and a molding film covering the connection substrate.
In Paragraph 3, The above molding film covers the upper surface of the connecting substrate, and The above molding film is a semiconductor package that exposes the upper surface of the first semiconductor chip and the upper surface of the second semiconductor chip.
In Article 1, The first redistribution substrate comprises a first redistribution insulating layer and first redistribution patterns disposed within the first redistribution insulating layer, wherein Each of the above first rewiring patterns is a semiconductor package comprising a first wiring portion and a first via portion disposed on the first wiring portion.
In Article 5, The conductive pattern further comprises a lower surface of the lowest first redistribution pattern among the above first redistribution patterns, wherein The above-mentioned challenge pattern includes a first challenge pattern and a second challenge pattern spaced apart from the first rewiring pattern at the lowest part with the first challenge pattern in between, and The first conductivity pattern is a semiconductor package comprising a material different from the first rewiring pattern and the second conductivity pattern.
In Article 1, The second redistribution substrate comprises a second redistribution insulating layer and a second redistribution pattern disposed within the second redistribution insulating layer, wherein The above second rewiring pattern is a semiconductor package comprising a second wiring portion and a second via portion disposed on the second wiring portion.
Package substrate; An interposer substrate disposed on the above-mentioned package substrate, wherein the interposer substrate comprises a first redistribution substrate, a second redistribution substrate on the lower surface of the first redistribution substrate, and an interposer molding film interposed between the first redistribution substrate and the second redistribution substrate; A connecting semiconductor chip mounted on the lower surface of the first redistribution substrate and disposed within the interposer molding film, wherein the connecting semiconductor chip has a first surface adjacent to the second redistribution substrate and a second surface adjacent to the first redistribution substrate; and A first semiconductor chip mounted on the upper surface of the first redistribution board, wherein The above interposer molding film is interposed between the second redistribution substrate and the first surface of the connection semiconductor chip, and The above interposer molding film is a semiconductor package interposed between the first redistribution substrate and the second surface of the connected semiconductor chip.
In Article 8, The chip stack is further included, mounted on the interposer substrate and horizontally spaced apart from the first semiconductor chip. The above chip stack is a semiconductor package comprising a plurality of stacked second semiconductor chips.
Package substrate; An interposer substrate disposed on the above-mentioned package substrate, wherein the interposer substrate comprises a first redistribution substrate, a second redistribution substrate on the lower surface of the first redistribution substrate, and an interposer molding film interposed between the first redistribution substrate and the second redistribution substrate; A connecting board disposed on the upper surface of the first redistribution board, wherein the connecting board has a connecting hole penetrating its interior; A first semiconductor chip mounted on the upper surface of the first rewiring board, wherein the first semiconductor chip is disposed within the connection hole; A second semiconductor chip mounted on the upper surface of the first rewiring board, wherein the second semiconductor chip is horizontally spaced apart from the first semiconductor chip, and the second semiconductor chip is disposed within the connection hole; A connecting semiconductor chip mounted on the lower surface of the first redistribution board and disposed within the interposer molding film; A capacitor chip mounted on the lower surface of the first redistribution board, disposed within the interposer molding film, and horizontally spaced apart from the connection semiconductor chip; and A molding film disposed on the interposer substrate and covering the sidewall of the first semiconductor chip, the sidewall of the second semiconductor chip, and the connecting substrate. The above interposer molding film covers the upper surface of the connected semiconductor chip and the lower surface of the connected semiconductor chip, and The above interposer molding film is a semiconductor package that covers the upper surface and the lower surface of the capacitor chip.

Description

Semiconductor package The present invention relates to a semiconductor package and a method for manufacturing the same, and more specifically, to a semiconductor package including a redistribution substrate and a method for manufacturing the same. A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, semiconductor packages involve mounting the semiconductor chip onto a printed circuit board (PCB) and electrically connecting them using bonding wires or bumps. With the recent advancement of the electronics industry, semiconductor packages are evolving in various directions with the goals of miniaturization, weight reduction, and manufacturing cost reduction. Furthermore, as their applications expand to include high-capacity storage devices, a wide variety of semiconductor packages are emerging. FIG. 1 is a plan view for illustrating a semiconductor package according to embodiments of the present invention. FIG. 2 is a drawing for explaining a semiconductor package according to embodiments of the present invention, and is a cross-sectional view along I-I' of FIG. 1. Figure 3 is an enlarged view of area A of Figure 2. Figures 4a and 4b are enlarged views of area B of Figure 2. FIGS. 5 to 14 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to embodiments of the present invention. FIG. 15 is a drawing for illustrating a semiconductor package according to embodiments of the present invention, and is a cross-sectional view along I-I' of FIG. 1. Hereinafter, in order to explain the present invention more specifically, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings. FIG. 1 is a plan view illustrating a semiconductor package according to embodiments of the present invention. FIG. 2 is a cross-sectional view along I-I' of FIG. 1 illustrating a semiconductor package according to embodiments of the present invention. FIG. 3 is an enlarged view of region A of FIG. 2. FIG. 4a and FIG. 4b are enlarged views of region B of FIG. 2. Referring to FIGS. 1, FIGS. 2, FIGS. 3, FIGS. 4a, and FIGS. 4b, the semiconductor package (10) may include a package substrate (100), an interposer substrate (200), a first semiconductor chip (310), a second semiconductor chip (320), a connecting semiconductor chip (330), a connecting substrate (400), and a molding film (460). A package substrate (100) may include substrate pads (110) and terminal pads (120). For example, the package substrate (100) may be a printed circuit board (PCB). The substrate pads (110) may be adjacent to the upper surface of the package substrate (100), and the terminal pads (120) may be adjacent to the lower surface of the package substrate (100). The substrate pads (110) may be exposed on the upper surface of the package substrate (100). Substrate wiring (not shown) may be provided within the package substrate (100). The substrate pads (110) and the terminal pads (120) may be electrically connected to the substrate wiring (not shown). In this specification, electrically connecting/connecting two components may include the components being connected/connected directly or indirectly through other conductive components. The substrate pads (110) and terminal pads (120) may include a conductive metal material, and may include at least one metal among copper (Cu), aluminum (Al), tungsten (W), and titanium (Ti). External terminals (150) may be provided on the lower surface of the package substrate (100). The external terminals (150) may be disposed on the lower surface of the terminal pads (120) and electrically connected to each of the terminal pads (120). The external terminals (150) may be connected to an external device. Accordingly, external electrical signals may be transmitted to and received on the substrate pads (110) through the external terminals (150). The external terminals (150) may include solder balls or solder bumps. The external terminals (150) may include a conductive metal material and may include at least one metal selected from tin (Sn), lead (Pb), silver (Ag), zinc (Zn), nickel (Ni), gold (Au), copper (Cu), aluminum (Al), and bismuth (Bi). An interposer substrate (200) may be disposed on the package substrate (100). The interposer substrate (200) may be disposed between the package substrate (100) and the first semiconductor chip (310), and between the package substrate (100) and the second semiconductor chip (320). The interposer substrate (200) may include a first redistribution substrate (210), a second redistribution substrate (220), and an interposer molding film (260). The interposer molding film (260) may be interposed between the first redistribution substrate (210) and the second redistribution substrate (220). The first redistribution substrate (210) may be disposed between the first semiconductor chip (310) and the interposer molding film (260).