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KR-102961648-B1 - MEMORY DEVICES AND METHODS FOR OPERATING THE SAME

KR102961648B1KR 102961648 B1KR102961648 B1KR 102961648B1KR-102961648-B1

Abstract

A memory device comprises a plurality of memory cells and a plurality of evaluation elements, and each evaluation element is connectable to a memory cell of the memory device. The memory device further comprises an interconnection unit configured to connect a plurality of memory cells to a first allocation of evaluation elements in a first state and to connect the same plurality of memory cells to a second allocation of evaluation elements in a second state, wherein, in the second state, at least one of the plurality of memory cells is connected to a different evaluation element. The memory device comprises an evaluation unit configured to control the interconnection unit from the first state to the second state. The evaluation unit is configured to evaluate a plurality of memory cells to obtain a first evaluation result in the first state and to evaluate a plurality of memory cells to obtain a second evaluation result in the second state.

Inventors

  • 오터스테트, 얀
  • 알러스, 볼프

Assignees

  • 인피니온 테크놀로지스 아게

Dates

Publication Date
20260508
Application Date
20210915
Priority Date
20200922

Claims (20)

  1. As a memory device, Multiple memory cells (12); Multiple evaluation elements (14) — each evaluation element (14) can be connected to a memory cell (12) of the memory device —; An interconnection unit (16) configured to connect the plurality of memory cells (12) to a first allocation of evaluation elements (14) in a first state, and to connect the same plurality of memory cells (12) to at least a second allocation of the evaluation elements (14) in a second state — in the second state, at least one of the plurality of memory cells (12) is connected to a different evaluation element (14) —; and Evaluation unit (18) configured to control the above interconnection unit (16) to transition from (i) the first state in which the at least one memory cell is not connected to the different evaluation element to (ii) the second state in which the at least one memory cell is connected to the different evaluation element. Includes, A memory device configured such that the evaluation unit (18) evaluates the plurality of memory cells (12) in the first state to obtain a first evaluation result (44 1 ) and evaluates the plurality of memory cells (12) in the second state to obtain a second evaluation result (44 2 ).
  2. In paragraph 1, A memory device in which, in the first state and the second state, each of the plurality of memory cells (12) is connected to an evaluation element (14).
  3. In paragraph 1 or 2, A memory device in which the first evaluation result (44 1 ) represents a first bit sequence, the second evaluation result (44 2 ) represents a second bit sequence, and the evaluation unit (18) is configured to provide the first bit sequence and the second bit sequence as bits of the same order.
  4. In paragraph 3, The above interconnection unit (16) includes reordering logic for implementing the first assignment and the second assignment, and A memory device configured such that the evaluation unit (18) includes a reverse reordering logic (22), and the reverse reordering logic (22) is reversed with respect to the reordering logic and changes the allocation of an evaluation element (14) for a bit position from the first state to the second state in reverse with respect to the reordering logic, thereby maintaining the bit position of the value read from the memory cell (12) in the first bit sequence and the second bit sequence without changing.
  5. In paragraph 1 or 2, A memory device configured such that the evaluation unit determines that the number of first bit errors in the first evaluation result (44 1 ) exceeds the number of errors that can be corrected by an error correction code used to store information in the plurality of memory cells (12), determines that the number of second bit errors in the second evaluation result is less than or equal to the number of errors that can be corrected by the error correction code, and uses the second evaluation result (44 2 ) as a result of a read operation of the memory device.
  6. In paragraph 1 or 2, The memory device is configured to determine the result of a read operation of the plurality of memory cells (12) using an error detection code.
  7. In paragraph 1 or 2, A memory device configured such that the evaluation unit (18) determines that the number of first bit errors in the first evaluation result (44 1 ) exceeds a predefined threshold and controls the interconnection unit (16) to the second state based on the number of bit errors.
  8. In paragraph 1 or 2, The evaluation unit (18) obtains at least a third evaluation result of the plurality of memory cells (12) by using a third allocation of evaluation elements (14) for the plurality of memory cells (12) in a third state, or To determine the combination evaluation result as a common majority vote judgment for the above plurality of memory cells or a group-specific majority vote judgment for groups of memory cells. Composed of, A memory device having at least one memory cell in each group of memory cells.
  9. In paragraph 1 or 2, The above evaluation unit (18) is configured to repeat a read operation using different assignments of evaluation elements (14) for memory cells (12) until an accurate or correctable read result is obtained or until a termination criterion occurs, in a memory device.
  10. In paragraph 1 or 2, The above evaluation unit (18) is configured to store error information (32) indicating that a specific pair of memory cells (12) and evaluation elements (14) are susceptible to error in a memory (28) accessible by the memory device.
  11. In paragraph 1 or 2, A memory device configured such that the evaluation unit (18) reads error information (32) from the memory (28) indicating that a specific pair of memory cells (12) and evaluation elements (14) among the plurality of memory cells is susceptible to error, and obtains a second evaluation result (44 2 ) based on the first evaluation result (44 1 ) being based on the specific pair, and/or avoids the specific pair when evaluating the plurality of memory cells (12).
  12. In paragraph 1 or 2, A memory device comprising at least one evaluation element (14) including a sensing amplifier.
  13. In paragraph 1 or 2, A memory device in which the plurality of memory cells (12) are implemented to provide one bit of information per memory cell, or are implemented as multi-level storage, or are implemented as multi-cell storage.
  14. In paragraph 1 or 2, The above evaluation unit is configured to determine the deviation between the evaluation result of at least the first evaluation element (14 1 ) of the first evaluation and the evaluation result of the second evaluation element (14 2 ) of the second evaluation, which are used for the same memory cell ( 12 1 ) , determine deviation information (33) that indicates the deviation between the evaluations of the memory cell (12 1), and store the deviation information (33) in the memory (28) of the memory device.
  15. In paragraph 1 or 2, The memory device is configured to read deviation information (33) from memory (28), — said deviation information indicates a deviation between the behaviors of evaluation elements (14) — and to use said deviation information (33) to correct the first evaluation result (44 1 ) or the second evaluation result (44 2 ).
  16. As a memory device, Multiple memory cells (12); Multiple evaluation elements (14) — each evaluation element (14) can be connected to a memory cell (12) of the memory device —; An interconnection unit (16) configured to connect the plurality of memory cells (12) to a first allocation of evaluation elements (14) in a first state, and to connect the same plurality of memory cells (12) to a second allocation of the evaluation elements (14) in a second state — in the second state, at least one of the plurality of memory cells (12) is connected to a different evaluation element (14) —; An evaluation unit (18) configured to control the above interconnection unit (16) to transition from (i) the first state in which at least one memory cell is not connected to the different evaluation element to (ii) the second state in which at least one memory cell is connected to the different evaluation element; and A memory (28) that stores error information (32) indicating that a reading operation using a specific pair of memory cells (12) and evaluation elements (14) among the plurality of memory cells in the first state is susceptible to error. Includes, A memory device configured such that the evaluation unit (18) reads the error information (32) from the memory (28) and obtains the evaluation result of the plurality of memory cells based on a reading operation using the second state based on the error information (32).
  17. As a memory device, memory cell (12); Multiple evaluation elements (14) — each evaluation element can be connected to the memory cell (12) of the memory device —; An interconnection unit (16) configured to connect the memory cell (12) to a first evaluation element (14 1 ) rather than a second evaluation element (14 2 ) in a first state, and to connect the memory cell to a second evaluation element (14 2 ) rather than the first evaluation element (14 1 ) in a second state; and An evaluation unit (18) configured to obtain a first evaluation result of the memory cell (12) in the first state and obtain a second evaluation result of the memory cell (12) in the second state Includes, The above evaluation unit (18) is configured to determine the deviation between the first evaluation result and the second evaluation result, and to store the deviation information (33) in the memory (28) of the memory device.
  18. As a method (700) for operating a memory device, The above memory device includes a plurality of memory cells and a plurality of evaluation elements, and each evaluation element is connectable to a memory cell of the memory device, and The above method is, A step (710) of connecting the plurality of memory cells in the first state to the first allocation of evaluation elements; A step (720) of connecting identical multiple memory cells in a second state to a second allocation of the evaluation elements, so that in the second state, at least one memory cell among the multiple memory cells is connected to a different evaluation element; and A step (730) of evaluating the plurality of memory cells in the first state in which at least one memory cell is not connected to the different evaluation factor to obtain a first evaluation result, and evaluating the plurality of memory cells in the second state in which at least one memory cell is connected to the different evaluation factor to obtain a second evaluation result. A method including
  19. As a method (800) for operating a memory device, The above memory device includes a plurality of memory cells and a plurality of evaluation elements, and each evaluation element is connectable to a memory cell of the memory device, and The above method is, A step (810) of connecting the plurality of memory cells in the first state to the first allocation of evaluation elements; A step (820) of connecting identical multiple memory cells in a second state to a second allocation of the evaluation elements, so that in the second state, at least one memory cell among the multiple memory cells is connected to a different evaluation element; and A step (830) of reading error information from memory indicating that a read operation using a specific pair of memory cells and evaluation elements among the plurality of memory cells is susceptible to error in the first state in which at least one memory cell is not connected to the different evaluation elements, and obtaining an evaluation result of the plurality of memory cells based on a read operation using the second state in which at least one memory cell is connected to the different evaluation elements based on the error information. A method including
  20. As a method (900) for operating a memory device, The above memory device includes a memory cell and a plurality of evaluation elements, and each evaluation element is connectable to the memory cell of the memory device, and The above method is, A step (910) of connecting a memory cell to a first evaluation element rather than a second evaluation element in a first state, and obtaining a first evaluation result of said memory cell; A step (920) of connecting the memory cell to the second evaluation element, rather than the first evaluation element, in a second state, and obtaining the second evaluation result of the memory cell; A step (930) of determining the deviation between the first evaluation result and the second evaluation result to obtain deviation information; Step (940) of storing the above deviation information in memory A method including

Description

Memory Devices and Methods for Operating the Same The present disclosure relates to memory devices, methods for operating memory devices, and computer programs for implementing such methods. In particular, the present disclosure relates to sensing amplifier reordering for memory rereading. Memory devices may include multiple memory cells. Memory cells may be evaluated by evaluation factors. Exemplary memory cells include transistors, resistive cells, etc. These cells may be written to or programmed and read. Reading a memory cell may include evaluating physical parameters of the cell, such as a voltage or potential detectable in the cell, a current flowing through the cell, and/or an electrical resistance that can be measured. It is necessary to operate memory devices reliably. In this regard, the technology forming the background of the present invention is described in U.S. Patent Application Publication No. 2010/0281340 and No. 2018/0033495. According to an example, a memory device comprises a plurality of memory cells, a plurality of evaluation elements, and an interconnection unit, wherein each evaluation element is connectable to a memory cell of the memory device, and the interconnection unit is configured to connect a plurality of memory cells to a first allocation of evaluation elements in a first state, and to connect the same plurality of memory cells to at least a second allocation of evaluation elements in a second state. In the second state, at least one of the plurality of memory cells is connected to a different evaluation element. The memory device further comprises an evaluation unit configured to control the interconnection unit from the first state to the second state. The evaluation unit is configured to evaluate a plurality of memory cells to obtain a first evaluation result in the first state, and to evaluate a plurality of memory cells to obtain a second evaluation result in the second state. According to an example, a memory device includes a plurality of memory cells and a plurality of evaluation elements, and each evaluation element is connectable to a memory cell of the memory device. The memory device includes an interconnection unit, and the interconnection unit is configured to connect a plurality of memory cells to a first allocation of evaluation elements in a first state, and to connect the same plurality of memory cells to a second allocation of evaluation elements in a second state. In the second state, at least one of the plurality of memory cells is connected to a different evaluation element. The device further includes an evaluation unit configured to control the interconnection unit from the first state to the second state. The device further includes a memory, and the memory stores error information indicating that a read operation using a specific pair of memory cells and an evaluation unit among the plurality of memory cells in the first state is susceptible to error. The evaluation unit is configured to read the error information from the memory and obtain an evaluation result of the plurality of memory cells based on a read operation using the second state based on the error information. According to an example, a memory device comprises a memory cell, a plurality of evaluation elements, an interconnection unit, and an evaluation unit, each evaluation element being connectable to a memory cell of the memory device, and the interconnection unit is configured to connect the memory cell to the first evaluation element in a first state and to connect the memory cell to the second evaluation element in a second state, and the evaluation unit is configured to obtain a first evaluation result of the memory cell in a first state and to obtain a second evaluation result of the memory cell in a second state. The evaluation unit is configured to determine deviation information between the first evaluation result and the second evaluation result and to store the deviation information in the memory of the memory device. Additional examples relate to methods and computer programs for operating memory devices. Additional examples are defined in dependent claims. Now, examples will be explained below with reference to the attached drawings. FIG. 1a illustrates a schematic block diagram of a memory device according to an example and in a first state. FIG. 1b illustrates a schematic block diagram of the memory device of FIG. 1a in a second state. FIG. 2a illustrates a schematic block diagram of a memory device in a first state according to an additional example. FIG. 2b illustrates a schematic block diagram of the memory device of FIG. 2a in a second state. FIG. 3 illustrates a schematic block diagram of a memory device according to an example having reordering logic and reverse reordering logic. FIG. 4 illustrates a schematic block diagram of a memory device according to an example having a memory for reading and/or writing error information. FIG. 5a illustrates a schematic diag