KR-102961671-B1 - SELF SELECTABLE resistive random access memory AND THE METHOD THEREOF

KR102961671B1KR 102961671 B1KR102961671 B1KR 102961671B1KR-102961671-B1

Abstract

The present invention provides a self-selective resistance change memory when integrated into a memory array and a method for manufacturing the same by implementing complementary resistance switching characteristics by mixing a complementary resistance change material, such as solid electrolyte chalcogenide nanoparticles or metal particles, into an active channel layer.

Inventors

장재원
이원용

Assignees

경북대학교 산학협력단

Dates

Publication Date: 20260507
Application Date: 20241211

Claims (15)

Substrate; A lower electrode layer formed on the above substrate; An active channel layer with changing resistance formed on the upper part of the lower electrode layer; and It includes an upper electrode layer formed on top of the above active channel layer, and The above active channel layer is, It is formed as a solid electrolyte-based electrochemical metallization cell (EMC) comprising solid electrolyte nanoparticles or nanoparticles synthesized from the solid electrolyte nanoparticles and one or more metal nanoparticles, and The above solid electrolyte-based electrochemical metallization cell is, Complementary resistance switching without a selector or reverse series arrangement by the movement of metal ions through an oxidation-reduction reaction with the above-mentioned oxidizable upper electrode layer and the above-mentioned lower electrode layer Resistance change memory.
In paragraph 1, The above active channel layer is, It is a single active layer, and The above solid electrolyte nanoparticles are, It comprises one or more nanoparticles of Ag x S, Ag x Se, Ag x Te, Ag x I, Sn x S , Sn x Se, Sn x Te, Sn x I, Cu x S, Cu x Se, Cu x Te, and Cu x I, The above metal nanoparticles are, Comprising one or more nanoparticles of Ag, Sn, and Cu, Resistance change memory.
In paragraph 1, The above active channel layer is, In a matrix of at least one active channel layer material among a dielectric material having a high k dielectric constant, a binary metal oxide, a transition metal oxide, and a lanthanide metal oxide, One or more of the above-mentioned solid electrolyte nanoparticles among Ag x S, Ag x Se, Ag x Te, Ag x I, Sn x S, Sn x Se, Sn x Te, Sn x I, Cu x S, Cu x Se, Cu x Te, and Cu x I; One or more of the metal nanoparticles among Ag, Sn, and Cu; and Nanoparticles synthesized from one or more of the solid electrolyte nanoparticles among Ag x S, Ag x Se, Ag x Te, Ag x I, Sn x S , Sn x Se, Sn x Te, Sn x I, Cu x S, Cu x Se, Cu x Te, and Cu x I, and one or more of the metal nanoparticles among Ag, Sn, and Cu Formed as a mixed single active channel layer Resistance change memory.
In paragraph 1, The above active channel layer is, First active channel layer; A second active channel layer formed on top of the first active channel layer; and A third active channel layer formed on top of the second active channel layer. Formed as a multistage active channel layer including Resistance change memory.
In paragraph 4, The first active channel layer and the third active channel layer are, Formed from at least one active channel layer material among a dielectric material having a high k dielectric constant, a binary metal oxide, a transition metal oxide, and a lanthanide metal oxide, and The second active channel layer above is, One or more of the solid electrolyte nanoparticles among Ag x S, Ag x Se, Ag x Te, Ag x I, Sn x S, Sn x Se, Sn x Te, Sn x I, Cu x S, Cu x Se, Cu x Te, and Cu x I are placed on top of the first active channel layer; One or more of the above-mentioned solid electrolyte nanoparticles among Ag x S, Ag x Se, Ag x Te, Ag x I, Sn x S, Sn x Se, Sn x Te, Sn x I, Cu x S, Cu x Se, Cu x Te, and Cu x I; or One or more of the metal nanoparticles of Ag, Sn, and Cu Formed as a thin film having complementary resistance switching characteristics using any one of the nanoparticles Resistance change memory.
In paragraph 1, The above active channel layer is, A thin film formed by any one of spin coating, printing, roll-to-roll printing, dip coating, and slot die coating methods Resistance change memory.
In paragraph 1, The upper electrode layer and the lower electrode layer above are, Comprising one or more metal nanoparticles among Ag, Au, Cu, and Ni Resistance change memory.
Step of preparing solid electrolyte nanoparticles and metal nanoparticles; Step of forming a lower electrode layer; A step of forming an active channel layer on the lower electrode layer in which the resistance changes using the solid electrolyte nanoparticles or a composite of the solid electrolyte nanoparticles and the metal nanoparticles; and The method includes the step of forming an upper electrode layer on top of the active channel layer, and The step of forming the active channel layer above is, A thin film of a solid electrolyte-based electrochemical metallization cell (EMC) comprising the above-mentioned solid electrolyte nanoparticles, wherein the active channel layer having complementary resistance switching characteristics according to an applied voltage without a selector or reverse series arrangement is formed by the movement of metal ions through a redox reaction with the above-mentioned oxidizable upper electrode layer and the above-mentioned lower electrode layer. Method for manufacturing resistance change memory.
In paragraph 8, Among the steps of preparing the solid electrolyte nanoparticles and metal nanoparticles, the step of preparing the solid electrolyte nanoparticles is, A metal salt as a solid electrolyte nanoparticle precursor and a nonmetal anhydride as a nonmetal precursor are each dissolved in a solvent to produce a metal salt solution and a nonmetal anhydride solution, and After mixing a capping agent into the above metal salt solution, the pH is adjusted, and Synthesizing solid electrolyte nanoparticles by mixing the non-metal anhydride solution with the metal salt solution mixed with the capping agent and pH adjusted, and reacting the metal with the non-metal. Method for manufacturing resistance change memory.
In paragraph 8, The upper electrode layer and the lower electrode layer above are, Comprising one or more metal nanoparticles among Ag, Au, Cu, and Ni Method for manufacturing resistance change memory.
In paragraph 8, The step of forming the active channel layer above is, A single active channel layer applied with one or more of the solid electrolyte nanoparticles selected from Ag x S, Ag x Se, Ag x Te, Ag x I, Sn x S , Sn x Se , Sn x Te, Sn x I, Cu x S, Cu x Se, Cu x Te, and Cu x I; or The active channel layer is formed as any one of a single active channel layer in which one or more of the solid electrolyte nanoparticles selected from Ag x S, Ag x Se , Ag x Te, Ag x I, Sn x S, Sn x Se, Sn x Te, Sn x I, Cu x S, Cu x Se, Cu x Te, and Cu x I are mixed with one or more of the metal nanoparticles selected from Ag, Sn, and Cu. Method for manufacturing resistance change memory.
In paragraph 8, The step of forming the active channel layer above is, One or more of the above-mentioned solid electrolyte nanoparticles among Ag x S, Ag x Se, Ag x Te, Ag x I, Sn x S, Sn x Se, Sn x Te, Sn x I, Cu x S, Cu x Se, Cu x Te, and Cu x I; One or more of the metal nanoparticles among Ag, Sn, and Cu; and A single active channel layer formed by mixing one or more of the solid electrolyte nanoparticles among Ag x S, Ag x Se, Ag x Te, Ag x I , Sn x S, Sn x Se , Sn x Te, Sn x I, Cu x S, Cu x Se, Cu x Te, and Cu x I with one or more of the nanoparticles synthesized from one or more of the metal nanoparticles among Ag, Sn, and Cu. Method for manufacturing resistance change memory.
In paragraph 8, The step of forming the active channel layer above is, First active channel layer; A second active channel layer formed on top of the first active channel layer; and The step of forming a multistage active channel layer including a third active channel layer formed on top of the second active channel layer. Method for manufacturing resistance change memory.
In Paragraph 13, The first active channel layer and the third active channel layer are, Formed from at least one active channel layer material among a dielectric material having a high k dielectric constant, a binary metal oxide, a transition metal oxide, and a lanthanide metal oxide, and The second active channel layer above is, One or more of the solid electrolyte nanoparticles among Ag x S, Ag x Se, Ag x Te, Ag x I, Sn x S, Sn x Se, Sn x Te, Sn x I, Cu x S, Cu x Se, Cu x Te, and Cu x I are placed on top of the first active channel layer; One or more of the above-mentioned solid electrolyte nanoparticles among Ag x S, Ag x Se, Ag x Te, Ag x I, Sn x S, Sn x Se, Sn x Te, Sn x I, Cu x S, Cu x Se, Cu x Te, and Cu x I; or One or more of the metal nanoparticles of Ag, Sn, and Cu A thin film formed with complementary resistance switching characteristics using any one of the nanoparticles Method for manufacturing resistance change memory.
In paragraph 8, The step of forming the active channel layer above is, A step of forming the active channel layer by any one of spin coating, printing, roll-to-roll printing, dip coating, and slot die coating methods. Method for manufacturing resistance change memory.

Description

Self-selectable resistive random access memory and method of manufacturing the same The present invention relates to a resistance change memory, and more specifically, to a self-selective resistance change memory when integrated into a memory array and a method for manufacturing the same. Flash memory, which is responsible for the storage portion in the process of storing and processing external signals, has reached its scaling limit due to physical limitations. In order to process large amounts of information simultaneously in real time in the Fourth Industrial Revolution, Resistive Random Access Memory (RRAM) devices are attracting attention as neuromorphic artificial intelligence memory that mimics human processing methods to solve the inefficiency of processing using conventional flash memory. RRAM is a memory device that utilizes a change in resistance and has a structure in which an insulator layer is located between the upper electrode and the lower electrode layer. Depending on the voltage, a filament is formed in the insulator layer, and the device exhibits switching characteristics such as SET, which changes from an off state with high resistance to an on state with low resistance, and RESET, which is the opposite process. The crossbar structure of a single-unit RRAM device is generally used to fabricate integrated RRAM arrays. However, the moment an integrated array with a crossbar structure connecting single RRAM devices is constructed, a sneak path current is generated, and to suppress this, the selector requires the connection of additional transistors and diodes. Alternatively, the sneak path current can be suppressed by stacking RRAMs in reverse series for integration. This presents a problem that causes limitations on device integration and spatial processing speed. FIG. 1 is a cross-sectional view showing the structure of an RRAM of an embodiment of the present invention. FIG. 2 is a drawing showing an active channel layer (30) that is a single active channel layer (310) of solid electrolyte nanoparticles or a mixture of solid electrolyte nanoparticles and metal nanoparticles. FIG. 3 is a drawing showing a multi-stage active channel layer (320) in which the active channel layer (30) is multi-stage. FIG. 4 is a flowchart showing the processing steps of a resistance change memory manufacturing method according to an embodiment of the present invention. Figures 5(a) and 5(b) are transmission electron microscope (TEM) images of Ag x Te synthesized nanoparticles (NP) before the annealing process, and the inset in Figure 5(b) is a diagram showing the electron diffraction pattern in a selected region of the synthesized Ag x Te NP (Nano Particle). Figure 6 is a graph showing the grain boundary angle incident X-ray diffraction spectra of Ag x Te thin films annealed at various temperatures. Figure 7 is a graph showing the Ag 3d and Te 3d X-ray photoelectron spectra of Ag x Te thin films as a function of various annealing temperatures. Figure 8 is a diagram showing atomic force microscope images of Ag x Te thin films annealed at various temperatures and their corresponding RMS (mean square) values. Figure 9(a) is an image of a fabricated Ag x Te-based RRAM array. The inset is an enlarged optical image of the fabricated Ag x Te RRAM device. Figures 9(b) to (d) are graphs showing the IV characteristics of an RRAM device fabricated based on Ag x Te NPs annealed at room temperature, 100 °C, and 200 °C, respectively. Figure 10 is a graph showing the threshold voltage extracted as a function of annealing temperature, where (a) is V th1 and V th2 and (b) is V th3 and V th4 . Figure 11 is a graph showing (a) endurance and (b) retention among the non-volatile characteristics of a complementary resistance switching Ag x Te RRAM device. Figure 12 is a graph showing representative IV characteristics of a fabricated Ag x Te-based RRAM device in the case of a) no compliance current (CC) and b) compliance current (CC). FIG. 13 is an SEM image of the active channel region of an Ag/Ag x Te/Au RRAM device in the case where (a) CC is 3 mA and (b) CC is absent after sweeping from 3.0 V to +3.0 V several times, and (c) and (d) are diagrams showing complementary resistance switching and bipolar resistance switching of the Ag x Te RRAM device, respectively. The present invention is not limited or restricted by the embodiments of the invention described with reference to the accompanying drawings and the contents described in the accompanying drawings. The terms used herein are for describing the embodiments and are not intended to limit the invention. In this specification, the singular form includes the plural form unless specifically stated otherwise in the text. As used herein, "comprises" and/or "comprising" do not exclude the presence or addition of one or more other components, steps, actions, and/or elements to the mentioned components, steps, actions, and/or elements. As used herein, terms such as “examples,” “exam