KR-102961696-B1 - Reducing compiler type checking costs through thread guessing and hardware transactional memory

Abstract

Systems, devices, and methods may provide a technique for generating a first compiler output based on input code containing dynamically typed variable information and generating a second compiler output based on input code, wherein the second compiler output includes type checking code for verifying one or more type inferences associated with the first compiler output. This technique may also execute the first compiler output and the second compiler output in parallel through different threads.

Inventors

• 장, 스위
• 딩, 쥔융
• 리, 톈유
• 하기가트, 모하메드, 알.

Assignees

• 인텔 코포레이션

Dates

Publication Date

20260508

Application Date

20191008

Claims (20)

1. As a performance-enhanced computing system, A network controller for obtaining an input code containing dynamically typed variable information; A processor coupled to the above network controller; and Memory coupled to the above processor - the above memory includes a set of instructions - Includes, and when the above instructions are executed by the processor, cause the computing system: Generate a first compiler output based on the above input code, and Generating a second compiler output based on the above input code - the second compiler output includes type checking code for verifying one or more type inferences associated with the first compiler output -, The above first compiler output and second compiler output are executed in parallel through different threads, and A computing system comprising a first compiler output further including fallback code for transitioning the computing system to an execution state independent of the one or more type inferences when the verification of the one or more type inferences by the second compiler output fails.
2. A computing system according to claim 1, wherein when the instructions are executed, the computing system additionally synchronizes communications between the first compiler output and the second compiler output through one or more shared memory objects.
3. In paragraph 2, in order to synchronize the communications, the instructions cause the computing system when executed: Through the first shared memory object, the transaction execution code within the first compiler output is notified whether the verification of the one or more type inferences by the second compiler output was successful; Notifying the spinlock code in the first compiler output whether the verification of the one or more type inferences was successful by the second compiler output through the second shared memory object, Computing system.
4. In paragraph 1, A computing system comprising: transaction execution code for suspending one or more tasks of the first compiler output when the verification of one or more type inferences by the second compiler output fails; spinlock code for keeping the first compiler output in a waiting state until the verification of one or more type inferences by the second compiler output is confirmed by the second compiler output; and memory storage code for storing one or more results of the transaction execution code in memory.
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6. In any one of claims 1 to 4, the computing system further comprises a first processor core and a second processor core, and to execute the first compiler output and the second compiler output in parallel, when the instructions are executed, the computing system: Executing the first compiler output in a first thread running on the first processor core; A second thread running on the second processor core that executes the second compiler output Computing system.
7. As a semiconductor device, One or more substrates; and Logic coupled to one or more substrates The logic comprises, wherein the logic is at least partially implemented in one or more of configurable logic or fixed-function hardware logic, and the logic is coupled to the one or more substrates: Generate a first compiler output based on input code containing dynamically typed variable information; Generate a second compiler output based on the above input code - the second compiler output includes type checking code for verifying one or more type inferences associated with the first compiler output -; The above first compiler output and second compiler output are executed in parallel through different threads, and A semiconductor device wherein the first compiler output further includes fallback code for transitioning the computing system to an execution state independent of the one or more type inferences when the verification of the one or more type inferences by the second compiler output fails.
8. A semiconductor device according to claim 7, wherein the logic coupled to one or more substrates synchronizes communications between the first compiler output and the second compiler output through one or more shared memory objects.
9. In paragraph 8, the logic coupled to the one or more substrates is: Notifying the transaction execution code within the first compiler output whether the verification of the one or more type inferences by the second compiler output was successful through the first shared memory object; Notifying the spinlock code in the first compiler output whether the verification of the one or more type inferences by the second compiler output was successful, through the second shared memory object Semiconductor device.
10. In Paragraph 7, A semiconductor device comprising: a transaction execution code for suspending one or more tasks of the first compiler output when the verification of one or more type inferences by the second compiler output fails; a spinlock code for keeping the first compiler output in a waiting state until the verification of one or more type inferences by the second compiler output is confirmed by the second compiler output; and a memory storage code for storing one or more results of the transaction execution code in memory.
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12. In any one of claims 7 to 10, the logic coupled to the one or more substrates is: Execute the first compiler output in a first thread running on a first processor core; Executing the second compiler output in a second thread running on a second processor core, Semiconductor device.
13. As at least one computer-readable storage medium comprising a set of instructions, When the above instructions are executed by a computing system, the computing system: Generate a first compiler output based on input code containing dynamically typed variable information; Generating a second compiler output based on the above input code - said second compiler output includes type checking code for verifying one or more type inferences associated with said first compiler output -; The above first compiler output and second compiler output are executed in parallel through different threads, and At least one computer-readable storage medium, wherein the first compiler output further comprises fallback code for transitioning the computing system to an execution state independent of the one or more type inferences when the verification of the one or more type inferences by the second compiler output fails.
14. In paragraph 13, at least one computer-readable storage medium that, when the instructions are executed, causes the computing system to additionally synchronize communications between the first compiler output and the second compiler output through one or more shared memory objects.
15. In paragraph 14, in order to synchronize the above communications, the above instructions cause the computing system when executed: Through the first shared memory object, the transaction execution code within the first compiler output is notified whether the verification of the one or more type inferences by the second compiler output was successful; Notifying the spinlock code in the first compiler output whether the verification of the one or more type inferences was successful by the second compiler output through the second shared memory object, At least one computer-readable storage medium.
16. In Paragraph 13, At least one computer-readable storage medium comprising: transaction execution code for suspending one or more tasks of the first compiler output when verification of one or more type inferences by the second compiler output fails; spinlock code for keeping the first compiler output in a waiting state until verification of one or more type inferences by the second compiler output is confirmed by the second compiler output; and memory storage code for storing one or more results of the transaction execution code in memory.
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18. In any one of paragraphs 13 through 16, in order to execute the first compiler output and the second compiler output in parallel, when the instructions are executed, the computing system: Execute the first compiler output in a first thread running on a first processor core; A second thread running on a second processor core that executes the second compiler output, At least one computer-readable storage medium.
19. As a method of operating a just-in-time (JIT) compiler device, A step of generating a first compiler output based on an input code containing dynamically typed variable information; A step of generating a second compiler output based on the above input code - the second compiler output includes type checking code for verifying one or more type inferences associated with the first compiler output -; and Step of executing the above first compiler output and second compiler output in parallel through different threads Includes, A method comprising: the first compiler output further including fallback code for transitioning the JIT compiler device to an execution state independent of the one or more type inferences when the verification of the one or more type inferences by the second compiler output fails.
20. A method according to claim 19, further comprising the step of synchronizing communications between the first compiler output and the second compiler output through one or more shared memory objects.

Description

Reducing compiler type checking costs through thread guessing and hardware transactional memory The embodiments generally relate to compiler technology. More specifically, the embodiments relate to the reduction of compiler type check costs through thread speculation and hardware transactional memory. Computer programming languages provide the use of variables to retrieve data, perform actions, output data, and so on. During the compilation of an application written in a given programming language, the types of variables used in the application can influence specific code optimization decisions made by the compiler. Applications written in dynamically typed languages, such as JavaScript, Python, and Ruby, typically have variable type information that is known only at runtime (and, for example, not at compile time). The lack of variable type information at compile time can result in applications running much slower than those written in statically typed languages. For example, when a code path optimized for integer addition is more efficient (however, for example, integer type information is not known at compile time), conventional solutions can compile a dynamically typed application into a generic code path structured to handle strings, floating-point numbers, double precision numbers, and all other variable types. While just-in-time (JIT) compilation techniques can increase execution speed when combined with type inference and/or speculation, significant room for improvement remains. For example, current approaches to implementing type checking code (e.g., to verify type inferences made during compilation) can introduce processing overhead that offsets the benefits of JIT compilation and type inference/speculation. The various advantages of the embodiments will become apparent to those skilled in the art by reading the following specification and appended claims and by referring to the following drawings. Figure 1 is a comparison block diagram of a compiler execution architecture according to an example and an embodiment of a conventional compiler execution architecture. FIG. 2 is a block diagram of an example of intended code according to an embodiment. FIG. 3 is a flowchart of an example of the operation method of a compiler device according to an embodiment. FIG. 4 is a flowchart of an example of a method for synchronizing communications between a first compiler output and a second compiler output according to an embodiment. Figure 5 is a comparison diagram of an example of conventional compiler output and a compiler output according to an embodiment. FIG. 6 is a diagram of an example of the execution flow when type checks according to an embodiment are passed. FIG. 7 is a diagram of an example of an execution flow when type checks according to an embodiment fail. FIG. 8 is a block diagram of an example of a performance-enhanced computing system according to an embodiment. FIG. 9 is an illustration of an example of a semiconductor device according to an embodiment. FIG. 10 is a block diagram of an example of a processor according to an embodiment. FIG. 11 is a block diagram of an example of a multiprocessor-based computing system according to an embodiment. Now, looking at FIG. 1, a conventional execution architecture (20) is illustrated in which a processor core (22) ("Core 1") executes compiler output (24) (24a-24c) including type checking code (24a), "intended" code (24b) (e.g., payload code for retrieving data, performing operations, and outputting data), and fallback code (24c). In the illustrated example, the type checking code (24a) verifies one or more type inferences made by a compiler (not illustrated) to optimize the intended code (24b) which produces results (26) when executed. If the illustrated type checking code (24a) determines that at least one of the type inference(s) is incorrect, the type checking code (24a) may trigger the execution of fallback code (24c) which produces results (28) without relying on the incorrect type inference(s). Of particular note is that the illustrated type checking code (24a), intended code (24b), and fallback code (24c) are executed sequentially on the same processor core (22) (e.g., on the same thread and/or task). As a result, the conventional execution architecture (20) may execute the compiler output (24) relatively slowly, particularly when the type checking code (24a) has a relatively high processing overhead (e.g., due to a large number of branches). In fact, if the type inference(s) are often correct, the overhead/cost associated with the type checking code (24a) may often be unnecessary. Additionally, because the type checking code (24a) is included in the same instruction execution stream as the intended code (24b), the compiler output (24) may consume a relatively large amount of cache space (e.g., Level 1/L1 instruction cache/I-cache). In contrast, the enhanced execution architecture (30) may include a first processor core (32) ("Core 1") that