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KR-102961720-B1 - Test socket and method of the same

KR102961720B1KR 102961720 B1KR102961720 B1KR 102961720B1KR-102961720-B1

Abstract

The present invention relates to a test socket and a method for manufacturing the same. The test socket for testing electrical conductivity of a memory array in which a plurality of memory dies are stacked in sequence comprises: a frame having an area formed in an inner region between a first direction on a plane and a second direction having a predetermined angle with respect to the first direction; at least one through hole formed in the frame to position at least one bump connected to the memory array; and at least one cantilever having an area and a thickness, extending from the frame inwardly to the through hole to contact the bump positioned in the through hole.

Inventors

  • 오재환

Assignees

  • 주식회사 인투시

Dates

Publication Date
20260511
Application Date
20250730

Claims (20)

  1. In a test socket for testing electrical conductivity of a memory array in which multiple memory dies are stacked in sequence, A frame having an area formed in an internal region between a first direction on a plane and a second direction having a predetermined angle with respect to the first direction; At least one through hole formed in the frame to position at least one bump connected to the memory array; and It includes at least one cantilever having an area and thickness that extends from the frame toward the inside of the through hole to contact the bump located in the through hole, A test socket characterized by including the frame and the cantilever being integrally formed.
  2. In paragraph 1, A test socket characterized in that the above-mentioned cantilever is formed from at least one alloy selected from an elastic nickel-iron (Ni-Fe) alloy, a nickel-cobalt (Ni-Co) alloy, and an iron-nickel-cobalt (Fe-Ni-Co) alloy.
  3. In paragraph 2, A test socket characterized by the cantilever applying a force of 0 gf and 0.2 gf or less to the bump when in contact with the bump.
  4. In Paragraph 1, A test socket characterized in that at least one side of the cantilever has the same level as at least one side of the frame.
  5. delete
  6. In Paragraph 1, An insulating layer is formed on each of the above frame and the above cantilever, and A test socket characterized by having a conductive layer formed on the insulating layer.
  7. In paragraph 6, A test socket characterized in that the conductive layer is formed of at least one material selected from Ag, Cu, Pd, and Au.
  8. In paragraph 6, The above conductive layer A first conductive layer in contact with a first bump located in a first through hole; and It includes a second conductive layer in contact with a second bump located in a second through hole different from the first through hole, and A test socket characterized in that the first conductive layer and the second conductive layer are electrically insulated so as not to move electric charge.
  9. In Paragraph 1, A test socket characterized by the thickness of the cantilever being formed to be 1㎛ to 20㎛.
  10. In Paragraph 1, The above test socket is A test socket characterized in that the above cantilever can test the conductivity of the memory array through contact or non-contact with the above bump.
  11. In paragraph 1, A test socket characterized in that the above-described cantilever has a trench or uneven pattern formed on its upper or lower surface to distribute stress received in the area where the cantilever and the frame are connected.
  12. In paragraph 1, A test socket characterized in that the cantilever has a trench or uneven pattern formed on its left and right sides, which can distribute the stress received in the area where the cantilever and the frame are connected.
  13. In Paragraph 1, The above test socket is A test socket characterized by further including a bump stopper disposed between a base die electrically connected to the memory array and a connection layer located below the base die to prevent at least one cantilever different from the cantilever in contact with the bump from directly contacting the connection layer.
  14. In Paragraph 13, A test socket characterized in that the bump stopper is extended along the longitudinal direction and is positioned between the test socket and the connection layer.
  15. In paragraph 1, The above cantilever is A test socket characterized by the central portion of the end being formed in a convex round shape, a concave round shape, a protruding angular shape, or a recessed angular shape.
  16. In Paragraph 1, A test socket characterized in that at least one end of one of the multiple cantilevers has a shape different from that of the other cantilevers.
  17. In paragraph 1, In the case where the above cantilever is formed in multiple numbers, A test socket characterized in that one cantilever has a different length from the other cantilever.
  18. In paragraph 1, A test socket characterized in that the edge shape of the through hole is formed as a closed shape, such as a circle, polygon, or curve.
  19. a) a step of etching a substrate on which an etching barrier film or a photoresist is formed as a pattern to form one or more trench patterns; b) a step of forming a socket structure layer by injecting a material to form a socket structure into the trench pattern above; c) a step of flattening the upper surface of the socket structure layer; d) a step of removing a portion of the substrate to expose the lower surface of the socket structure layer so as to form a frame, at least one through hole formed in the frame, and at least one cantilever extended from the frame toward the inner direction of the through hole; e) forming an insulating layer on the completely exposed socket structure layer; f) A step of forming a mask pattern on the upper and lower surfaces of the insulating layer; g) forming a preliminary conductive layer on the insulating layer on which the mask pattern is formed; and h) A method for manufacturing a test socket characterized by including the step of removing the above mask pattern to form a socket structure having a conductive layer in which the first conductive layer and the second conductive layer are electrically insulated from each other.
  20. In Paragraph 19, In the case where step a) above forms a double trench pattern a-1) A step of etching the substrate having the first etching barrier formed thereon to form a first trench pattern; a-2) A step of forming a second etching barrier film that exposes a portion of the lower surface of the first trench pattern; and a-3) A method for manufacturing a test socket characterized by including the step of etching the substrate having the second etching barrier formed thereon to form a second trench pattern having a width smaller than the width of the lower surface of the first trench pattern.

Description

Test socket and method of manufacturing the same The present invention relates to a test socket and a method for manufacturing the same, and more particularly to a test socket and a method for manufacturing the same that can reduce the defect rate in the subsequent process by minimizing deformation of microbumps having small and soft characteristics when the test socket is directly contacted to microbumps in the memory stack structure of High Bandwidth Memory (HBM) to check for normal electrical operation. High Bandwidth Memory (HBM) rapidly increases data processing speeds by stacking DRAM vertically, enabling the rapid processing and transmission of large amounts of data. The demand for such high-bandwidth memory is increasing rapidly due to the need for high-performance computing as technologies such as AI, big data, autonomous driving, and smart services advance. High bandwidth memory transmits and receives signals through through-silicon vias (TSVs) formed by penetrating each of the stacked DRAMs, and may be configured to include an interposer electrically connecting the HBM and the substrate at the bottom of the stacked DRAM structure, a logic die electrically connected to the interposer, a CPU/GPU/SOC die, and a package substrate. As the number of stacked layers of the high bandwidth memory increases, the chip spacing decreases, and the wafer thickness becomes increasingly thin. Consequently, the size of the bumps electrically connected to the through-silicon vias is gradually decreasing to function as inter-chip bonding and signal input/output terminals. Meanwhile, high-bandwidth memory forms a memory stack by stacking individual DRAM chips vertically after inspection, but the memory stack must be inspected again in order for the memory stack to be connected to the interposer, system chip, and package substrate without defects. Examples of vertical probe technologies having pogo pins, silicone rubber, and elasticity for inspecting high-bandwidth memory are disclosed in the following patent documents 1 to 3, etc. The following patent document 1 relates to a test probe for inspecting electrical characteristics of semiconductor and MEMS processes and a method for manufacturing the same, comprising the steps of: laminating a lower dry film on a substrate and forming a terminal body portion by filling a molding groove of the lower dry film with a predetermined material; laminating an upper dry film on the upper surface of the lower dry film and forming a tip portion by filling a predetermined material above the terminal body portion within the molding groove of the upper dry film; processing the upper part of the tip portion to form at least one tip; and removing the upper dry film and the lower dry film from the tip portion formed with the tip and the terminal body portion. Patent Document 2 below relates to an electrical probe used for testing integrated circuits, wherein the skate on the tip of the probe for testing electrical devices is a probe tip contact portion with reduced thickness, and the probe tip is formed with a smooth curved surface, and presents a technology that solves the problem of the short lifespan of a multilayer skate probe due to mechanical wear during testing operations. Meanwhile, the test socket disclosed in Patent Document 3 below is disposed between a semiconductor device and a test device and conducts current between the terminal of the semiconductor device and the pad of the test device, and is disclosed for a test socket comprising: a sheet-type connector made of an insulating sheet having through holes formed at each position corresponding to the terminal of the semiconductor device; a plurality of conductive parts formed at each through hole of the sheet-type connector; an insulating support part disposed on the lower side of the sheet-type connector; a plurality of conductive elastic parts formed such that one end contacts each conductive part below the plurality of conductive parts and extends to penetrate the insulating support part so that the other end contacts the pad of the test device; and a plurality of elastic bodies disposed between the conductive elastic parts, with one end coupled to the insulating sheet and the other end coupled to the insulating support part, wherein each conductive elastic part has an empty space formed around it except for the part penetrating the insulating support part. Figure 1 is a schematic diagram illustrating the general structure of a high-bandwidth memory. FIG. 2 is a drawing showing a test socket according to a first embodiment of the present invention. Figure 3 is a diagram showing the structure to be inspected by the test socket of Figure 2. FIG. 4 is a drawing for explaining a method of inspecting a structure to be inspected using a test socket according to a first embodiment of the present invention. Figure 5 is a drawing showing a cross-section taken by cutting along the cutting line A-A' of Figure 1. FIG. 6 is a diagram i