KR-102961857-B1 - CIRCUIT BOARD AND PACKAGE SUBSTRATE HAVING THE SAME

KR102961857B1KR 102961857 B1KR102961857 B1KR 102961857B1KR-102961857-B1

Abstract

A circuit board according to an embodiment comprises: a first insulating layer; a first circuit pattern layer disposed on the first insulating layer; and a second insulating layer disposed on the first insulating layer and the first circuit pattern layer and including a cavity, wherein the first circuit pattern layer includes a first pad portion perpendicularly overlapping the cavity and on which a chip is mounted; and a connecting portion connected to the first pad portion, wherein the connecting portion includes a first portion perpendicularly overlapping the cavity; and a second portion not perpendicularly overlapping the cavity.

Inventors

이동건
강태규
유호돌

Assignees

엘지이노텍 주식회사

Dates

Publication Date: 20260507
Application Date: 20210916

Claims (20)

First insulating layer; A second insulating layer disposed on the first insulating layer and including a cavity; and It includes a first circuit pattern layer disposed between the first insulating layer and the second insulating layer, and The first circuit pattern layer above is, A first pad portion disposed in a first region of the first insulating layer that is vertically superimposed with the cavity and corresponds to the bottom surface of the cavity; A second pad portion disposed in a second region of the first insulating layer covered by the second insulating layer, which is not vertically overlapped with the cavity; and It includes a connecting portion that overlaps vertically with the inner wall of the cavity and connects the first pad portion and the second pad portion, The above connecting portion includes a first portion disposed in the first region that overlaps vertically with the cavity and a second portion disposed in the second region that does not overlap vertically with the cavity, and directly connects the first pad portion and the second pad portion between the first insulating layer and the second insulating layer. Circuit board.
In paragraph 1, The width of the first pad portion is greater than the width of the connection portion, and The above connection part includes a trace, Circuit board.
In paragraph 1, One end of the first part of the above-mentioned connecting portion is in direct contact with the first pad portion, and One end of the second part of the above-mentioned connecting portion is in direct contact with the second pad portion, Circuit board.
In paragraph 1, The inner wall of the above cavity is, A slope surface comprising such that the horizontal width of the cavity gradually decreases as it faces the first insulating layer, Circuit board.
In paragraph 4, At least a portion of the above-mentioned connection is perpendicularly overlapped with the above-mentioned inclined surface, Circuit board.
In paragraph 5, The inclined surface of the second insulating layer is, An overlapping region vertically overlapping with a first circuit pattern layer including the above-mentioned connection portion; and A non-overlapping region that is not vertically overlapped with the first circuit pattern layer, Circuit board.
In any one of paragraphs 1 through 6, The first and second parts of the above-mentioned connecting portion are located on the same plane, and The upper surface of the second part of the above connection is covered with the second insulating layer. Circuit board.
In any one of paragraphs 1 through 6, The above first insulating layer comprises a first insulating material, and The second insulating layer comprises a second insulating material different from the first insulating material, Circuit board.
In paragraph 8, The first insulating layer above includes prepreg, and The second insulating layer above includes PID (Photoimageable diodes), Circuit board.
In any one of paragraphs 1 through 6, A first conductive coupling portion disposed on the first pad portion; and A chip comprising a chip disposed on the first conductive coupling portion, Circuit board.
In Paragraph 10, A second circuit pattern layer disposed on the second insulating layer; and It includes a second conductive coupling portion disposed on the second circuit pattern layer, and The uppermost part of the second conductive coupling portion is, Located lower than the top of the above chip, Circuit board.
In any one of paragraphs 1 through 6, The first insulating layer and the second insulating layer comprise the same first insulating material, The above first insulating material includes PID (Photoimageable dielectics), and The bottom surface of the above cavity is, Positioned higher than the lower surface of the first pad portion and positioned lower than the upper surface of the first pad portion, Circuit board.
In Paragraph 12, The first circuit pattern layer protrudes above the upper surface of the first insulating layer, and The above second insulating layer is, A supporting insulating member that is vertically superimposed with the above cavity and disposed between the first pad portion and the connecting portion, Circuit board.
In Paragraph 13, The thickness of the above-mentioned supporting insulating portion satisfies a range between 20% and 95% of the thickness of the first circuit pattern layer, Circuit board.
In Paragraph 12, It includes a third insulating layer disposed below the second insulating layer, and The third insulating layer comprises a second insulating material different from the first and second insulating layers, and The above second insulating material includes prepreg, Circuit board.
A first circuit board including a first cavity; A second circuit board coupled to the first circuit board, comprising a second cavity vertically overlapping with the first cavity; and It includes a chip disposed within the first cavity and the second cavity, The first circuit board above is, First insulating layer; A second insulating layer disposed on the first insulating layer and including the first cavity; and It includes a first circuit pattern layer disposed between the first insulating layer and the second insulating layer, and The first circuit pattern layer above is, A first pad portion disposed in a first region of the first insulating layer corresponding to the bottom surface of the first cavity and vertically superimposed with the first cavity; A second pad portion disposed in a second region of the first insulating layer covered by the second insulating layer, which is not vertically overlapped with the first cavity; and It includes a connecting portion that overlaps vertically with the inner wall of the first cavity and connects the first pad portion and the second pad portion, The above connecting portion includes a first portion disposed in a first region that overlaps vertically with the first cavity and a second portion disposed in a second region that does not overlap vertically with the first cavity, and directly connects the first pad portion and the second pad portion between the first insulating layer and the second insulating layer. The above chip includes a first overlapping region horizontally overlapping with the first cavity, and a second overlapping region horizontally overlapping with the second cavity. Package substrate.
In Paragraph 16, The uppermost part of the above chip is located higher than the first circuit board, Package substrate.
In paragraph 16 or 17, It includes a third circuit board disposed on the second circuit board, and The above third circuit board includes a memory chip, The above second circuit board is, An interposer substrate connecting the first circuit board and the third circuit board, Package substrate.
In paragraph 16 or 17, It includes a memory chip mounted on the second circuit board, and The second circuit board is a memory board connected to the first circuit board, Package substrate.
In paragraph 16 or 17, The first cavity above includes a first-1 cavity and a first-2 cavity spaced apart in the length direction or width direction, and The above chip is, A first chip disposed within the above-mentioned first-1 cavity, and It includes a second chip disposed within the first and second cavities, and The first circuit pattern layer includes a connection pattern connecting the first chip and the second chip, Package substrate.

Description

Circuit board and package substrate having the same An embodiment relates to a circuit board and a package board including the same. As the performance of electrical and electronic products advances, technologies are being proposed and researched to attach a larger number of packages to substrates of limited size. However, since conventional packages are based on mounting a single semiconductor chip, there are limitations in achieving the desired performance. A typical package substrate features a form in which a processor package housing a processor chip and a memory package housing memory chips are connected as a single unit. By manufacturing the processor and memory chips into a single integrated package, this type of package substrate offers the advantages of reducing the chip mounting area and enabling high-speed signals through short paths. Due to these advantages, the above-mentioned package substrate is widely applied to mobile devices and the like. Meanwhile, recently, due to the increasing specifications of electronic devices such as mobile devices and the adoption of HBM (High Bandwidth Memory), package sizes are growing larger, and consequently, package substrates including interposers are being primarily used. In this case, the interposer is composed of a silicon substrate. However, in the case of interposers such as silicon substrates, there is a problem in that not only is the material cost for manufacturing the interposer high, but the formation of TSV (Through Silicon Via) is also complex and expensive. In addition, conventionally, substrates containing silicon-based interconnect bridges have been used as package substrates. However, in the case of silicon-based interconnect bridges, reliability issues exist due to the Coefficient of Thermal Expansion (CTE) mismatch between the silicon material of the bridge and the organic material of the substrate, and there is a problem of degraded power integrity characteristics. Figure 1 is a cross-sectional view showing a package substrate according to a comparative example. FIG. 2 is a cross-sectional view showing a circuit board according to a first embodiment. FIG. 3a is a plan view of the circuit board of FIG. 2 with some components removed. FIG. 3b is a plan view showing the first circuit pattern layer in the state where the second insulating layer is arranged in FIG. 3a. FIG. 4a is a cross-sectional view of a circuit board including a cavity of the first comparative example. Figure 4b is a plan view of the circuit board of Figure 4a. FIG. 4c is a cross-sectional view of a circuit board including a cavity of the second comparative example. FIG. 5a is a drawing showing a circuit board according to a second embodiment. Figure 5b is a cross-sectional view of the circuit board of Figure 5a in the AA' direction of Figure 3b. FIG. 6 is a drawing showing a circuit board according to a third embodiment. FIG. 7 is a drawing showing a first package substrate according to an embodiment. FIG. 8 is a drawing showing a second package substrate according to an embodiment. FIG. 9 is a drawing showing a third package substrate according to an embodiment. FIG. 10 is a drawing showing a fourth package substrate according to an embodiment. FIGS. 11a to 11j are drawings showing the manufacturing method of the circuit board illustrated in FIG. 2 in the order of process. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted. Furthermore, terms used in the embodiments of the present invention (including technical and scientific terms) may be interpreted in a meaning generally understood by those skilled in the art to which the present invention pertains, unless explicitly and specifically defined otherwise. Terms commonly used, such as those defined in advance, may be interpreted by considering their meaning in the context of the relevant technology. Additionally, the terms used in the embodiments of the present invention are intended to describe the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text, and when described as "at least one of A and B and C (or more than one)," it may include one or more of all combinations that can be formed from A, B, and C. Additionally, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the embodiments of the present invention. These terms are intended merely to distinguish a component from other components and are not to limit the nature, order, or sequence of said co