KR-102961979-B1 - STORAGE DEVICE AND OPERATING METHOD THEREOF

Abstract

The present invention relates to an electronic device. A storage device comprising a memory device that provides information indicating whether operation is performed at a valid operating voltage to a memory controller according to the present invention, and a memory controller that controls the memory device, may include a memory device that generates valid level information indicating whether the voltage used to perform the operation is included in a valid voltage range, and a memory controller that provides a status read command requesting the result of performing the operation to the memory device, and controls the memory device to change the voltage used to perform the operation based on the valid level information included in the status read response provided from the memory device in response to the status read command.

Inventors

• 나충언

Assignees

• 에스케이하이닉스 주식회사

Dates

Publication Date

20260508

Application Date

20201117

Claims (20)

1. A memory cell array comprising a plurality of memory cells; Peripheral circuit that performs a read operation for sensing data stored in selected memory cells among the plurality of memory cells above; A lead level register containing information regarding the levels of lead voltages used in the above lead operation; A read operation processing unit that controls the peripheral circuit to sense data stored in the selected memory cells using the read voltages in response to a read command provided by a memory controller, and generates ready information indicating that the read operation is completed; A valid lead level information generation unit that generates valid lead level information indicating whether the lead voltages are included in a preset valid lead voltage range in response to the above lead command; and It includes a status register that stores status information including the above ready information and the above effective read level information, and A memory device in which, when the above valid read level information indicates that the above read voltages are not included in the above valid read voltage range, the read operation processing unit skips the read operation and stores the ready information in the status register.
2. In claim 1, the lead level register is, Includes reference lead level information and current lead level information, The above-mentioned read operation processing unit is, A memory device that updates the current read level information in response to a read voltage change command provided by the memory controller.
3. In Clause 2, the above reference lead level information is, Each includes information regarding the minimum lead levels and maximum lead levels of the above lead voltages, and The above current lead level information is, A memory device containing information on current read levels set by the memory controller.
4. In Clause 3, the effective read level information generating unit is, A memory device that, in response to the above read command, generates the result of determining whether the current read levels each have a value between the minimum read levels and the maximum read levels as the valid read level information.
5. In claim 4, the effective read level information generating unit is, A memory device that stores effective lead level information in a status register indicating that the current lead levels are within the effective lead voltage range, if each of the current lead levels is a value between the minimum lead levels and the maximum lead levels.
6. In claim 4, the effective read level information generating unit is, A memory device that stores valid lead level information in a status register indicating that the current lead levels are not within a valid lead voltage range if each of the current lead levels is not a value between the minimum lead levels and the maximum lead levels.
7. In Clause 2, the lead voltage change command is, A memory device that is either a parameter setting command or a feature setting command.
8. In Clause 2, the memory cell array is, A memory device further comprising a system block that stores the above-mentioned reference read level information.
9. In claim 8, the above-mentioned read operation processing unit is, A memory device that stores reference read level information obtained from the system block in the read level register when power is applied.
10. In claim 1, the read operation processing unit is, A memory device that provides state information to the memory controller in response to a state read command provided by the memory controller after the above read operation is performed.
11. A memory cell array comprising a plurality of memory cells; Peripheral circuit that performs a read operation for sensing data stored in selected memory cells among the plurality of memory cells above; A lead level register containing information regarding the levels of lead voltages used in the above lead operation; A valid read level information generating unit that generates valid read level information indicating whether the read voltages are included in a preset valid read voltage range in response to a read command input from a memory controller; A read operation processing unit that controls the peripheral circuit to sense data stored in the selected memory cells using the read voltages according to the effective read level information and generates ready information indicating that the read operation is completed; and It includes a status register that stores status information including the above ready information and the above effective read level information, and A memory device in which the read operation processing unit, in response to valid read level information that the read voltages are not included in a valid read voltage range, skips the operation of sensing data stored in the selected memory cells using the read voltages and stores the ready information in the status register.
12. In Clause 11, the above-mentioned read operation processing unit is, A memory device that controls the peripheral circuit to sense data stored in the selected memory cells using the read voltages in response to effective read level information indicating that the read voltages are included in a valid read voltage range.
13. delete
14. In Clause 11, the above-mentioned lead level register is, Includes reference lead level information and current lead level information, The above-mentioned read operation processing unit is, A memory device that updates the current read level information in response to a read voltage change command provided by the memory controller.
15. In Clause 14, the above reference lead level information is, Each includes information regarding the minimum lead levels and maximum lead levels of the above lead voltages, and The above current lead level information is, A memory device containing information on current read levels set by the memory controller.
16. In item 15, the above effective read level information generating unit is, A memory device that, in response to the above read command, generates the result of determining whether the current read levels each have a value between the minimum read levels and the maximum read levels as the valid read level information.
17. In Clause 16, the above-mentioned effective read level information generating unit is, A memory device that stores effective lead level information in a status register indicating that the current lead levels are within a valid lead voltage range, if each of the current lead levels is a value between the minimum lead levels and the maximum lead levels.
18. In Clause 16, the above-mentioned effective read level information generating unit is, A memory device that stores valid lead level information in a status register indicating that the current lead levels are not within a valid lead voltage range if each of the current lead levels is not a value between the minimum lead levels and the maximum lead levels.
19. In Clause 11, the above-mentioned read operation processing unit is, A memory device that provides state information to the memory controller in response to a state read command provided by the memory controller after the above read operation is performed.
20. A memory device that generates valid level information indicating whether the voltage used to perform the operation is included in a valid voltage range; and A memory controller that provides a status read command requesting the result of performing the above operation to the memory device, and controls the memory device to change the voltage used to perform the above operation based on the valid level information included in the status read response provided from the memory device in response to the status read command. A storage device that, when the above valid level information indicates that the above voltage is not included in the above valid voltage range, the memory device skips the above operation and stores state information including the above valid level information in a state register included in the memory device.

Description

Storage device and operating method thereof The present invention relates to an electronic device, and more specifically, to a storage device and a method of operating the same. A storage device is a device that stores data under the control of a host device, such as a computer or a smartphone. A storage device may include a memory device that stores data and a memory controller that controls the memory device. Memory devices can be classified into volatile memory devices and non-volatile memory devices. Volatile memory devices may be memory devices that store data only while power is supplied and lose the stored data when the power supply is cut off. Volatile memory devices may include Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), etc. Non-volatile memory devices are memory devices in which data is not lost even when the power is cut off, and include ROM (Read Only Memory; ROM), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), and Flash Memory. FIG. 1 is a drawing for explaining a storage device according to an embodiment of the present invention. Figure 2 is a drawing for explaining the memory device of Figure 1. Figure 3 is a diagram for explaining the structure of one of the memory blocks of Figure 2. Figure 4 is a diagram illustrating the threshold voltage distribution of a single-level cell. Figure 5 is a diagram illustrating the threshold voltage distribution of a multi-level cell. Figure 6 is a diagram illustrating the threshold voltage distribution of a triple-level cell. FIG. 7 is a drawing for explaining the configuration of a memory device according to an embodiment of the present invention. Figure 8 is a diagram illustrating the data stored in the read level register of Figure 7. Figure 9 is a diagram illustrating data communication between a memory controller and a memory device. Figure 10 is a diagram illustrating the status register of Figure 7. FIG. 11 is a diagram for explaining the operation of the read operation control unit and the read level management unit of the memory controller of FIG. 1. FIG. 12 is a diagram showing another embodiment of the memory controller of FIG. 1. FIG. 13 is a block diagram showing a memory card system to which a storage device according to an embodiment of the present invention is applied. FIG. 14 is a block diagram showing a Solid State Drive (SSD) system to which a storage device according to an embodiment of the present invention is applied. FIG. 15 is a block diagram showing a user system to which a storage device according to an embodiment of the present invention is applied. Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application. FIG. 1 is a drawing for explaining a storage device according to an embodiment of the present invention. Referring to FIG. 1, the storage device (50) may include a memory device (100) and a memory controller (200). The storage device (50) may be a device that stores data under the control of a host (400), such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system. Alternatively, the storage device (50) may be a device that stores data under the control of a host (400) that stores a large amount of data in one place, such as a server or data center. The storage device (50) can be manufactured as any one of various types of storage devices according to the host interface, which is the method of communication with the host (400). For example, the storage device (50) can be configured as any one of various types of storage devices such as an SSD, MMC, eMMC, RS-MMC, micro-MMC type multimedia card, SD, mini-SD, micro-SD type secure digital card, USB (universal serial bus) storage device, UFS (universal flash storage) device, PCMCIA (personal computer memory card international association) card type storage device, PCI (peripheral component interconnection) card type storage device, PCI-E (PCI express) card type storage device, CF (compact flash) card, smart media card, memory stick, etc. The storage device (50) can be manufactured in any one of various types of package forms. For example, the storage device (50) can be manufactured in any one of various types of package forms such as POP (package on package), SIP (system in package), SOC (system on chip), MCP (multi-chip package), COB (chip on board), WFP (wafer-level fabricated package), WSP (wafer-level stack package), etc. The memory device (100) can store data. The mem