KR-102962084-B1 - APPARATUS FOR GENERATING PIM OPERATION ADDRESSES AND METHOD THEREOF

Abstract

A method of operating an electronic device according to one embodiment includes the steps of generating a memory request regarding a Processing In Memory (PIM) operation, acquiring a PIM operation address in response to the memory request, and transmitting the memory request and the PIM operation address to a memory controller, wherein the PIM operation address may be a set of addresses that are shuffled into a preset target bank when the memory controller performs bank shuffling.

Inventors

• 차상훈
• 백윤아
• 김현수
• 이선정
• 최민정

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260511

Application Date

20241114

Claims (20)

1. In a method of operating an electronic device including a processor, The above processor generates a memory request regarding a PIM (Processing In Memory) operation; The above processor acquires a PIM operation address in response to the memory request; and The above processor transmits the memory request and the PIM operation address to the memory controller. Includes, The above PIM operation address is When the memory controller performs memory addressing including bank shuffling, it is a set of addresses that are shuffled into a preset target bank, and The step of obtaining the above PIM operation address is The processor obtains the PIM operation address based on one or more of a table storing the PIM operation address and a hash function used in the bank shuffling. including, Method of operation of an electronic device.
2. delete
3. In paragraph 1, The above table is Storing the row address where the target bank is output when the above bank shuffling is performed, Method of operation of an electronic device.
4. In paragraph 1, The above table is When performing the bank shuffling above, storing a pair of a row address from which the target bank is output and a bank address corresponding to the row address, Method of operation of an electronic device.
5. In paragraph 1, The step of obtaining the above PIM operation address is The processor performs bank shuffling based on the hash function to calculate a row address where the target bank can be output. including, Method of operation of an electronic device.
6. In paragraph 1, The step of obtaining the above PIM operation address is The processor performs the bank shuffling based on a DRAM addressing hash function used in the bank shuffling to calculate a pair of a low address where the target bank can be output and a bank address corresponding to the low address. including, Method of operation of an electronic device.
7. In paragraph 1, After the above-mentioned transfer step, the memory controller performs the bank shuffling to change the bank address of the PIM operation address to the target bank; and The memory controller generates a memory command including the PIM operation address changed through the bank shuffling and the memory request. A method of operating an electronic device, further comprising
8. In Paragraph 7, A step in which a router receives the memory command and determines whether the modified PIM operation address included in the memory command corresponds to any one of the predetermined designated memory addresses; and If the router corresponds to any one of the designated memory addresses, the router converts the modified PIM operation address into a redirect memory address mapped to the corresponding designated memory address based on mapping information stored in a routing register. A method of operating an electronic device, further comprising
9. In paragraph 8, The above mapping information maps each of the designated memory addresses representing a part of the memory to a redirect memory address representing another part of the memory, and The above memory command is executed at the above converted redirect memory address, Method of operation of an electronic device.
10. In Paragraph 9, When PIM operations are performed on a target PIM tile corresponding to the above-mentioned converted redirect memory address, a plurality of redirect memory addresses stored in the routing register are updated to a plurality of redirect memory addresses corresponding to the next PIM tile of the target PIM tile. Method of operation of an electronic device.
11. In paragraph 1, The above bank shuffling is including shuffling of banks or channels, Method of operation of an electronic device.
12. In electronic devices, Generate a memory request regarding PIM (Processing In Memory) operation, and In response to the above memory request, obtain the PIM operation address, and A processor that transmits the above memory request and the above PIM operation address to the memory controller Includes, The above PIM operation address is When the memory controller performs memory addressing including bank shuffling, it is a set of addresses that are shuffled into a preset target bank, and The above processor Acquiring the PIM operation address based on one or more of a table storing the PIM operation address and a hash function used in the bank shuffling, Electronic device.
13. delete
14. In Paragraph 12, The above table is Storing the row address where the target bank is output when the above bank shuffling is performed, Electronic device.
15. In Paragraph 12, The above table is When performing the bank shuffling above, storing a pair of a row address from which the target bank is output and a bank address corresponding to the row address, Electronic device.
16. In Paragraph 12, The above processor Based on the above hash function, performing the above bank shuffling to calculate a row address from which the target bank can be output, Electronic device.
17. In Paragraph 12, The above processor Based on the DRAM addressing hash function used in the bank shuffling above, performing the bank shuffling to calculate a pair of a row address where the target bank can be output and a bank address corresponding to the row address, Electronic device.
18. In Paragraph 12, Perform the bank shuffling above to change the bank address of the PIM operation address to the target bank, and generate a memory command including the PIM operation address changed through the bank shuffling and the memory request. The above memory controller including, Electronic device.
19. In Paragraph 18, Determining whether the modified PIM operation address included in the above memory command corresponds to any of the predetermined designated memory addresses, If the above modified PIM operation address corresponds to any one of the above designated memory addresses, the modified PIM operation address is converted into a redirect memory address mapped to the corresponding designated memory address based on the mapping information stored in the routing register. router including, Electronic device.
20. In Paragraph 19, The above mapping information maps each of the designated memory addresses representing a part of the memory to a redirect memory address representing another part of the memory, and The above memory command is executed at the above converted redirect memory address, Electronic device.

Description

Apparatus for Generating PIM Operation Addresses and Method of Operating Thereof Embodiments of the present invention relate to a PIM operation address generation device and a method of operation thereof. With the volume and speed of data processing increasing rapidly in recent years, various technologies are being researched to maximize data processing performance. Among these, Processing-in-Memory (PIM) technology is attracting attention as a key technology that accelerates data processing speeds by processing data directly within memory, thereby reducing bottlenecks caused by data transfer between the CPU and memory. The importance of this technology is becoming increasingly prominent, particularly in application fields requiring large-scale data processing or real-time analysis. Traditional systems utilize a structure where the CPU reads data from memory, performs calculations, and stores the results back into memory. However, this approach can lead to performance degradation due to frequent data transfers between the CPU and memory. To address this, PIM technology processes data within the memory itself, minimizing such data transfers, reducing bottlenecks, and enhancing overall system efficiency. PIM technology can be utilized in various application fields, and methods to maximize the efficiency of in-memory computations to implement this are continuously being researched. In particular, technologies that manage data locations within memory and optimize parallel processing across multiple banks are acting as important factors in determining PIM computation performance. The information described above may be provided as related art for the purpose of aiding understanding of the present disclosure. No claim or determination is made as to whether any of the foregoing may be applied as prior art related to the present disclosure. Figure 1 is a diagram illustrating a method to improve memory bandwidth through bank interleaving. Figure 2 is a diagram illustrating a method to solve the Bank Thrashing problem and maximize bank parallelism through Bank Shuffling. FIG. 3 is a drawing for explaining an electronic device according to one embodiment. FIG. 4 is a diagram illustrating a method for designating a row address as a PIM operation address according to one embodiment. FIG. 5 is a diagram illustrating a method of storing row addresses in a table (510) according to one embodiment. FIG. 6 is a diagram illustrating a method for designating a row address and a pair of bank addresses corresponding to the row address as PIM operation addresses according to one embodiment. FIG. 7 is a diagram illustrating a method of storing row address and bank address pairs in a table according to one embodiment. FIG. 8 is a drawing for explaining an electronic device according to one embodiment. FIGS. 9 and 10 are drawings illustrating examples of a routing table according to one embodiment. FIG. 11 is a diagram showing a method of operation of an electronic device according to one embodiment. FIG. 12 is a drawing showing an electronic device according to one embodiment. The specific structural or functional descriptions disclosed in this specification are illustrative of embodiments according to technical concepts only, and the actual implemented form may take various other forms and is not limited to the embodiments described in this specification. Terms such as "first" or "second" may be used to describe various components, but these terms should be understood solely for the purpose of distinguishing one component from another. For example, the first component may be named the second component, and similarly, the second component may be named the first component. When it is stated that one component is "connected" or "connected" to another component, it should be understood that while it may be directly connected or connected to that other component, there may also be other components in between. Conversely, when it is stated that one component is "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between. Expressions describing the relationships between components, such as "between" and "directly between," or "adjacent to" and "directly adjacent to," should be interpreted in the same way. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this specification, terms such as “comprising” or “having” are intended to specify the existence of the implemented features, numbers, steps, actions, components, parts, or combinations thereof, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art. Terms such as those defined in commo