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KR-102962130-B1 - GROUP Ⅲ NITRIDE DEVICE AND METHOD OF FABRICATING A GROUP Ⅲ NITRIDE-BASED DEVICE

KR102962130B1KR 102962130 B1KR102962130 B1KR 102962130B1KR-102962130-B1

Abstract

In an embodiment, the group III nitride-based transistor device comprises a first passivation layer disposed on a first main surface of a group III nitride-based layer, a second passivation layer disposed on the first passivation, a source ohmic contact, a drain ohmic contact, and a gate located on the first main surface of a group III nitride-based layer, and a field plate — the field plate is disposed laterally between the gate and the drain ohmic contact and is spaced apart from the gate and the drain ohmic contact —.

Inventors

  • 비르너 알버트
  • 브레치 헬무트
  • 트와이남 존

Assignees

  • 인피니언 테크놀로지스 아게

Dates

Publication Date
20260511
Application Date
20210427
Priority Date
20200428

Claims (15)

  1. As a method for manufacturing a group III nitride-based transistor, A step of providing a substrate comprising a group III nitride-based layer, a first passivation layer on a first main surface of the group III nitride-based layer, and a second passivation layer disposed on the first passivation layer — wherein the second passivation layer has a composition different from that of the first passivation layer — and, A step of forming a first ohmic contact and a second ohmic contact that extend at least partially through the first passivation layer on the first main surface of the group III nitride-based layer—wherein the first passivation layer extends between the first ohmic contact and the second ohmic contact, and the second passivation layer is disposed on the first ohmic contact and the second ohmic contact—and, The step of covering the first ohmic contact and the second ohmic contact with a first sublayer of passivation material, and A step of flattening to form a flattened intermediate surface including the surface of the first ohmic contact portion, the surface of the second ohmic contact portion, and the first sub-layer, and A step of forming a second sublayer of a passivation material disposed on the first ohmic contact portion and the second ohmic contact portion on the flattened intermediate surface — the first sublayer and the second sublayer form the second passivation layer — and, A step of forming a first mask layer on the second passivation layer — the first mask layer comprises a first insulating layer disposed on the second passivation layer and a first resist layer on the first insulating layer — and, A step of forming a first opening for a gate electrode in the first mask layer — the first opening extends through the first resist layer and the first insulating layer — and, A step of forming a second opening for a field plate in the first mask layer — said second opening extends through the first resist layer and the first insulating layer — and, A step of removing the second passivation layer exposed by the first opening to form a first via for the gate electrode — the first via has a base formed by the first passivation layer — and, A step of removing the second passivation layer exposed by the second opening to form a second via for the field plate — the second via has a base formed by the first passivation layer — and, The step of removing the first resist layer, and A step of applying a second resist layer on the first insulating layer, which covers the second opening for the field plate and leaves the first opening for the gate electrode and the region of the first insulating layer adjacent to the first opening uncovered; and A step of removing the first passivation layer exposed by the first via and increasing the depth of the first via so that the first via has a base formed by the group III nitride-based layer, and The step of removing the second resist layer, and A method comprising the step of depositing an electrically conductive material on the first via and the second via. Method for manufacturing a Group III nitride-based transistor.
  2. In Article 1, The second resist layer leaves a portion of the first insulating layer disposed adjacent to the first via exposed. Method for manufacturing a Group III nitride-based transistor.
  3. In Article 1 or Article 2, The base of the first via has a width of 50 nm to 400 nm, or the minimum distance between the base of the first via and the second via is 50 nm to 400 nm. Method for manufacturing a Group III nitride-based transistor.
  4. In Article 1 or Article 2, The first passivation layer comprises silicon nitride, the second passivation layer comprises silicon oxide, and the first insulating layer comprises titanium nitride, Method for manufacturing a Group III nitride-based transistor.
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  7. In Article 1, A step of forming a third opening in the first mask layer — the third opening extends through the first resist layer and the first insulating layer and is located over the second ohmic contact — and, The step of removing the second passivation layer exposed at the third opening and forming a third via having a base that exposes a portion of the second ohmic contact, and The step of covering the third via with the second resist layer, and The step of additionally depositing an electrically conductive material on the third via after removing the second resist layer, and The method further comprises the step of planarizing to form a planarized surface including isolated regions of an electrically conductive material located in the first via, the second via, and the third via — wherein each isolated region of the electrically conductive material is surrounded by the second passivation layer. Method for manufacturing a Group III nitride-based transistor.
  8. In Article 7, The step of forming a second insulating layer on the isolated region of the second passivation layer and the electrically conductive material, and A step of forming a third insulating layer on the second insulating layer — the second insulating layer and the third insulating layer have different compositions — and, A step of structuring the third insulating layer to form a first trench located over the first via — the first trench has a base spaced from the first via by a part of the third insulating layer and the second insulating layer, and the first trench is wider laterally than the first via — and, A step of forming a fourth via in the base of the first trench to expose the electrically conductive material of the first via by removing the third insulating layer and the second insulating layer — The above-mentioned fourth via is laterally smaller than the above-mentioned first trench — and, A method further comprising the step of depositing an electrically conductive material on the fourth via and the first trench. Method for manufacturing a Group III nitride-based transistor.
  9. In Article 8, A step of structuring the third insulating layer to form a second trench on the second via and a third trench on the third via — wherein the second trench has a base spaced apart from the second via by a part of the third insulating layer and the second insulating layer, and the second trench is wider laterally than the second via, and the third trench has a base spaced apart from the third via by a part of the third insulating layer and the second insulating layer, and the third trench is wider laterally than the third via — and, A step of forming a fifth via in the second trench to expose the electrically conductive material of the second via by removing the third insulating layer from the base of the second trench, and A step of forming a sixth via in the third trench to expose the electrically conductive material of the third via by removing the third insulating layer from the base of the third trench, and The method further comprises the step of depositing the electrically conductive material deposited in the fourth via and the first trench onto the second trench, the third trench, the fifth via, and the sixth via. Method for manufacturing a Group III nitride-based transistor.
  10. In Article 1 or Article 2, The above electrically conductive material is tungsten, Method for manufacturing a Group III nitride-based transistor.
  11. As a group III nitride-based transistor device, A first passivation layer disposed on the first main surface of a Group III nitride-based layer, and A second passivation layer disposed on the first passivation layer, and A source ohmic contact, a drain ohmic contact, and a gate located on the first main surface of the above-mentioned group III nitride-based layer — said gate comprising a gate via disposed transversely between the source ohmic contact and the drain ohmic contact and extending to the upper surface of the second passivation layer — and, Field plate ― said field plate is disposed laterally between said gate and said drain ohm contact, is spaced apart from said gate and said drain ohm contact, and extends to the upper surface of said second passivation layer ― and, A first via extending from the source ohmic contact to the upper surface of the second passivation layer, and A second via extending from the drain ohm contact to the upper surface of the second passivation layer — the second passivation layer covers the peripheral region of the source ohm contact and the drain ohm contact — and, It includes a first insulating layer that is substantially planar and disposed on the peripheral regions of the gate electrode, the field plate, the first via and the second via, and on the upper surface of the second passivation layer, and The field plate is substantially perpendicular to the first main surface and is electrically coupled to the source electrode by a lateral field plate redistribution structure that extends over the gate electrode and is spaced apart from the gate electrode, and The source electrode, the gate electrode, the drain electrode, and the field plate each have an elongated form and extend on the first main surface in a longitudinal direction substantially parallel to each other, and The above transverse field plate redistribution structure comprises a longitudinal section positioned on the field plate and extending substantially parallel to the longitudinal direction, and a plurality of transverse sections spaced apart in the longitudinal direction. Each transverse section extends over the gate electrode and is spaced apart from the gate electrode, and is electrically coupled to the field plate by a field plate conductive via. Group III nitride-based transistor device.
  12. In Article 11, The source ohmic contact comprises a base portion having a conductive surface, the conductive surface comprises a peripheral portion and a central portion, the peripheral portion and the central portion are substantially coplanar and have different compositions, and the first via is located on the central portion of the conductive surface and/or, The drain ohmic contact comprises a base portion having a conductive surface, the conductive surface comprises a peripheral portion and a central portion, the peripheral portion and the central portion are substantially coplanar and have different compositions, and the second via is located on the central portion of the conductive surface. Group III nitride-based transistor device.
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  15. In Article 11, The lateral gate redistribution structure further comprises a plurality of transverse sections extending substantially perpendicularly to the longitudinal direction, each transverse section being spaced apart from the gate electrode and electrically coupled to the gate electrode by a gate conductive via, and the transverse sections of the lateral gate redistribution structure being interleaved with the transverse sections of the lateral field plate redistribution structure. Group III nitride-based transistor device.

Description

Group III Nitride Device and Method of Fabricating a Group III Nitride-Based Device To date, transistors used in power electronics applications have generally been manufactured using silicon (Si) semiconductor materials. Common transistor devices for power applications include Si CoolMOS®, Si power MOSFETs, and Si Insulated Gate Bipolar Transistors (IGBTs). Recently, silicon carbide (SiC) power devices have been considered. Currently, Group III-N semiconductor devices, such as gallium nitride (GaN) devices, are emerging as attractive candidates because they deliver large currents, support high voltages, and offer very low on-resistance and fast switching times. However, further improvements to Group III nitride-based devices are desirable. According to the present invention, a method for manufacturing a group III nitride-based transistor comprises the steps of: providing a group III nitride-based layer, a first passivation layer on a first main surface of the group III nitride-based layer, and a second passivation layer disposed on the first passivation layer — the second passivation layer has a composition different from that of the first passivation layer —; forming a first mask layer on the second passivation layer — the first mask layer comprises a first insulating layer disposed on the second passivation layer and a first resist layer on the first insulating layer —; forming a first opening for a gate electrode in the first mask layer — the first opening extends through the first resist layer and the first insulating layer — and forming a second opening for a field plate in the first mask layer — the second opening is a first Extended through a resist layer and a first insulating layer — and a step of forming a first via for a gate electrode by removing a second passivation layer exposed by a first opening — the first via has a base formed by the first passivation layer — and a step of forming a second via for a field plate by removing a second passivation layer exposed by a second opening — the second via has a base formed by the first passivation layer — and a step of removing a first resist layer; a step of applying a second resist layer on a first insulating layer that covers the second opening for the field plate and leaves the region of the first insulating layer adjacent to the first opening for the gate electrode and the first opening uncovered; and a first exposed by the first via such that the first via has a base formed by a group III nitride multilayer structure The method includes the steps of removing a passivation layer and increasing the depth of the first via, removing a second resist layer, and depositing an electrically conductive layer on the first via and the second via. In some embodiments, the first resist layer is a photoresist layer and the second resist layer is a photoresist layer. In some embodiments, the electrically conductive layer is a tungsten layer. In some embodiments, the method further comprises the steps of depositing a tungsten layer on a second passivation layer transversely adjacent to the first via and the second via, and flattening to form a flattened surface comprising an isolated region of tungsten surrounded by the second passivation layer. In some embodiments, the second resist layer leaves a portion of the first insulating layer disposed adjacent to the first via exposed. In some embodiments, the first insulating layer and the first photoresist are patterned using deep ultra violet (DUV) technology. In some embodiments, the base of the first via has a width of 30 nm to 500 nm (e.g., about 250 nm or less) or a width of 225 nm to 350 nm (e.g., about 250 nm), and/or the minimum distance between the base of the first via and the base of the second via is 30 nm to 500 nm at the nearest point, or 225 nm to 350 nm, e.g., 250 nm or less. In some embodiments, the base of the first via and the base of the second via each have a width of 50 nm to 400 nm, or 200 nm to 350 nm, for example, about 250 nm, and the distance between the first via and the second via at the nearest point is 100 nm to 400 nm, or 200 nm to 350 nm, for example, about 250 nm. In some embodiments, the first passivation layer comprises silicon nitride, the second passivation layer comprises silicon oxide, and the first insulating layer comprises titanium nitride. In some embodiments, the substrate further comprises a first ohmic contact and a second ohmic contact on a first main surface of a group III nitride-based layer, a first passivation layer located on the first main surface of the group III nitride-based layer and extending between the first ohmic contact and the second ohmic contact, and a second passivation layer disposed on the first passivation layer, the first ohmic contact and the second ohmic contact. In some embodiments, the substrate comprises a first passivation layer disposed on a first main surface. In some embodiments, the method further comprises the steps of forming a first o