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KR-102962149-B1 - CHIP PACKAGE AND MANUFACTURING METHOD THEREFOR, AND CONDUCTIVE ADHESIVE FILM

KR102962149B1KR 102962149 B1KR102962149 B1KR 102962149B1KR-102962149-B1

Abstract

The present invention relates to a chip package, a method for manufacturing the same, and a conductive bonding film, wherein a conductive bonding film having a structure in which an Ag-based metal layer is thinly formed on the upper and lower surfaces of a Cu-based metal layer is formed, thereby lowering manufacturing costs and improving product competitiveness. The method for manufacturing a chip package according to the present invention may include a first step of transferring a first Ag-based metal layer onto the lower surface of a conductive metal layer of a semiconductor chip, a second step of transferring a Cu-based metal layer onto the lower surface of the first Ag-based metal layer, and a third step of transferring a second Ag-based metal layer onto the lower surface of the Cu-based metal layer.

Inventors

  • 맹재훈

Assignees

  • 주식회사 아모그린텍

Dates

Publication Date
20260508
Application Date
20230713

Claims (20)

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  2. A first step of transferring a first Ag-based metal layer onto the lower surface of a conductive metal layer of a semiconductor chip; A second step of transferring a Cu-based metal layer onto the lower surface of a first Ag-based metal layer; and A third step of transferring a second Ag-based metal layer onto the lower surface of the above Cu-based metal layer; is included, The above first step is, Step 1-1: Preparing a semiconductor chip having a conductive metal layer formed on its lower surface; Step 1-2 of stacking the semiconductor chip so that the conductive metal layer contacts the first Ag-based metal layer formed on the first base film and bonding it by applying pressure under a first pressure condition; and A method for manufacturing a chip package comprising a first-to-third step of separating the first Ag-based metal layer bonded to the conductive metal layer from the first base film.
  3. In paragraph 2, A method for manufacturing a chip package, further comprising the step of forming a first Ag-based metal layer on a first base film by applying an Ag paste and drying it on the first base film prior to the first-2 steps above.
  4. In paragraph 3, In the step of forming the first Ag-based metal layer, The above Ag paste comprises silver (Ag) powder and a binder, and The above silver powder comprises a first silver particle group, a second silver particle group, a third silver particle group, and a fourth silver particle group, and The first silver particle group, the second silver particle group, and the third silver particle group each have different average particle diameters (D50) and are flake-shaped particle groups having different average aspect ratio ranges, The above-mentioned fourth particle group is a spherical particle group, and the method for manufacturing a chip package.
  5. In paragraph 2, The pressure of the first pressurization condition above is in the range of 2 MPa or more and 3 MPa or less, and The temperature of the first pressurization condition above is in the range of 130℃ or higher and 180℃ or lower, and A method for manufacturing a chip package in which the time of the first pressurization condition is in the range of 1 second or more and 3 seconds or less.
  6. In paragraph 2, The above second step is, Step 2-1: stacking the semiconductor chip such that the lower surface of the first Ag-based metal layer contacts the Cu-based metal layer formed on the second base film and bonding it by applying pressure under a second pressure condition; and A method for manufacturing a chip package comprising a second step of separating the Cu-based metal layer bonded to the lower surface of the first Ag-based metal layer from the second base film.
  7. In paragraph 6, A method for manufacturing a chip package, further comprising the step of forming a Cu-based metal layer on a second base film by applying a Cu paste and drying it on the second base film prior to the above 2-1 step.
  8. In paragraph 6, The pressure of the second pressurization condition is higher than the pressure of the first pressurization condition, and A method for manufacturing a chip package in which the pressure of the second pressurization condition is higher than the temperature of the first pressurization condition.
  9. In paragraph 6, The pressure of the second pressurization condition above is in the range of 2 MPa or more and 5 MPa or less, and The temperature of the second pressurization condition above is in the range of 130℃ or higher and 180℃ or lower, and A method for manufacturing a chip package in which the time of the second pressurization condition is in the range of 1 second or more and 5 seconds or less.
  10. In paragraph 2, The above third step is, Step 3-1, wherein the semiconductor chip is laminated such that the lower surface of the Cu-based metal layer contacts the second Ag-based metal layer formed on the third base film, and the chip is bonded by applying pressure under a third pressure condition; and A method for manufacturing a chip package comprising a third-2 step of separating the second Ag-based metal layer bonded to the lower surface of the Cu-based metal layer from the third base film.
  11. In Paragraph 10, A method for manufacturing a chip package, further comprising the step of forming a second Ag-based metal layer on a third base film by applying an Ag paste and drying it on the third base film prior to the above 3-1 step.
  12. In Paragraph 11, In the step of forming the second Ag-based metal layer, The above Ag paste comprises silver (Ag) powder and a binder, and The above silver powder comprises a first silver particle group, a second silver particle group, a third silver particle group, and a fourth silver particle group, and The first silver particle group, the second silver particle group, and the third silver particle group each have different average particle diameters (D50) and are flake-shaped particle groups having different average aspect ratio ranges, The above-mentioned fourth particle group is a spherical particle group, and the method for manufacturing a chip package.
  13. In Paragraph 10, The pressure of the third pressurization condition is the same as the pressure of the first pressurization condition, and A method for manufacturing a chip package in which the temperature of the third pressurization condition is the same as the temperature of the first pressurization condition.
  14. In Paragraph 10, The pressure of the above third pressurization condition is in the range of 2 MPa or more and 3 MPa or less, and The temperature of the above third pressurization condition is in the range of 130℃ or higher and 180℃ or lower, and A method for manufacturing a chip package in which the time of the third pressurization condition is in the range of 1 second or more and 3 seconds or less.
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Description

Chip package and manufacturing method therefor, and conductive adhesive film The present invention relates to a chip package, a method for manufacturing the same, and a conductive bonding film, and more specifically, to a chip package formed to be bonded to a heat dissipation substrate and electrically connected, a method for manufacturing the same, and a conductive bonding film. For electronic products to operate, electrical signals must flow between the circuit board and electronic components. Conductive bonding films are designed to replace the soldering process with film bonding, enabling ultra-fine bonding that reduces product weight and provides thin, highly reliable bonding. Conductive bonding films are manufactured by mixing fine conductive particles into a polymer adhesive resin to form a film; however, such polymer adhesive resin films have problems such as poor adhesion to the substrate and difficulty in maintaining electrical properties. As an alternative, a silver film is manufactured by coating a paste containing a high concentration of silver particles to a desired thickness using coating equipment; however, there is a problem of low cost competitiveness due to the recent increase in the price of silver particles. The matters described in the background technology above are intended to aid in understanding the background of the invention and may include matters that are not disclosed prior art. FIG. 1 is a cross-sectional view showing a chip package according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a state in which a chip package according to an embodiment of the present invention is bonded to a heat dissipation substrate. FIG. 3 is a flowchart illustrating a method for manufacturing a chip package according to an embodiment of the present invention. FIG. 4 is a cross-sectional view illustrating the step of transferring a first Ag-based metal layer in a chip package manufacturing method according to an embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating the step of transferring a Cu-based metal layer in a chip package manufacturing method according to an embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating the step of transferring a second Ag-based metal layer in a chip package manufacturing method according to an embodiment of the present invention. FIG. 7 is a cross-sectional view illustrating a method of bonding a chip package to a heat dissipation substrate according to an embodiment of the present invention. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. The embodiments are provided to more fully explain the invention to those skilled in the art, and the following embodiments may be modified in various different forms, and the scope of the invention is not limited to the following embodiments. Rather, these embodiments are provided to make the disclosure more faithful and complete and to fully convey the spirit of the invention. The terms used herein are for describing specific embodiments and are not intended to limit the invention. Additionally, the singular form in this specification may include the plural form unless the context clearly indicates otherwise. In the description of the embodiments, where each layer (film), region, pattern, or structure is described as being formed "on" or "under" the substrate, each layer (film), region, pad, or pattern, "on" and "under" include both being formed "directly" and "indirectly" through another layer. In addition, the reference for the top or bottom of each layer is, in principle, based on the drawings. The drawings are intended solely to facilitate an understanding of the concept of the present invention and should not be interpreted as limiting the scope of the invention. Additionally, relative thicknesses, lengths, or sizes in the drawings may be exaggerated for convenience and clarity of explanation. FIG. 1 is a cross-sectional view showing a chip package according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a state in which a chip package according to an embodiment of the present invention is bonded to a heat dissipation substrate. Referring to FIGS. 1 and 2, a chip package (1) may be configured to include a semiconductor chip (100) having a conductive metal layer (110) formed on its lower surface and a conductive bonding film (200) bonded to the lower surface of the semiconductor chip (100). Here, the conductive bonding film (200) may be configured to include a first Ag-based metal layer (210), a Cu-based metal layer (220), and a second Ag-based metal layer (230). Such a chip package (1) may be bonded to a heat dissipation substrate (300). The semiconductor chip (100) may be a power semiconductor device that performs control processing such as DC/AC conversion of electrical energy, voltage, and frequency chan