KR-102962232-B1 - SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

Abstract

A semiconductor structure is provided. The semiconductor structure includes a functional cell region comprising an n-type functional transistor and a p-type functional transistor. The semiconductor structure also includes a first power transmission cell region comprising a first cut feature and a first contact rail within the first cut feature. The semiconductor structure also includes a first power rail electrically connected to the source terminal of the p-type functional transistor and the first contact rail of the first power transmission cell region. The semiconductor structure also includes a second power transmission cell region adjacent to the first power transmission cell region and comprising a second cut feature and a second contact rail within the second cut feature. The semiconductor structure also includes an insulating strip extending in a first direction from the first cut feature to the second cut feature.

Inventors

• 첸 주이-린
• 창 차오-유안
• 창 펑-밍
• 창 융-팅
• 왕 핑-웨이
• 팅 이-펭

Assignees

• 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드

Dates

Publication Date

20260507

Application Date

20231129

Priority Date

20230919

Claims (10)

1. As a method for forming a semiconductor structure: A step of forming an isolation structure surrounding a first active region; A step of forming a first dummy gate structure across the first active region and the isolation structure; A step of replacing at least a portion of the first dummy gate structure with an insulating strip; A step of forming a first cutting feature by penetrating the insulation strip and the isolation structure; A step of forming a first contact rail on the first cutting feature; A step of forming a first via rail that overlaps with the first contact rail in the first cutting feature; and Step of forming a first metal line that overlaps with the first via rail A method including
2. In paragraph 1, The method further includes the step of forming a second cutting feature by penetrating the insulation strip and the isolation structure, A method in which the first active region is located between the first cutting feature and the second cutting feature, and the insulating strip extends continuously from the first cutting feature to the second cutting feature.
3. In claim 1, after forming the first contact rail on the first cutting feature and before forming the first via rail that overlaps with the first contact rail on the first cutting feature, A step of polishing the first active region and the isolation structure to expose the surface of the first cutting feature from the rear. A method that further includes.
4. In paragraph 1, A method further comprising the step of forming a second metal line electrically connected to the first metal line on the contact rail, wherein the contact rail and the via rail are interposed vertically between the first metal line and the second metal line.
5. In claim 1, the step of replacing at least a portion of the first dummy gate structure with the insulating strip is: A step of etching the first dummy gate structure, the first active region, and the isolation structure to form a trench; and Step of forming a dielectric material within the above trench A method including
6. In claim 1, the step of forming the first via rail that overlaps the first contact rail on the first cutting feature is: A step of etching the first cutting feature to form a trench that exposes the surface of the first contact rail; and Step of filling the above trench with a conductive material A method including
7. In paragraph 1, A step of forming a second dummy gate structure across the first active region and the isolation structure; and The step of replacing the above-mentioned second dummy gate structure with a gate stack Includes more, A method in which the second dummy gate structure comprises a gate dielectric layer on the first active region and a metal gate electrode layer on the gate dielectric layer.
8. In paragraph 1, A step of forming the isolation structure surrounding the second active region; A step of forming a source/drain feature on the second active region - the first metal line is electrically connected to the source/drain feature -; and A step of forming a gate stack across the second active region and the isolation structure. A method that further includes.
9. As a method for forming a semiconductor structure: A step of forming a plurality of active regions on a substrate; A step of forming a plurality of insulating strips across the plurality of active regions - the plurality of insulating strips extend vertically into the substrate by penetrating the active regions -; A step of forming a first contact rail between a first active region and a second active region in the plurality of active regions, and forming a second contact rail between a second active region and a third active region in the plurality of active regions; A step of forming a cutting feature between the second active region and the fourth active region in the plurality of active regions above - wherein the first active region is formed in a first p-type well, the second active region and the fourth active region are formed in a second p-type well, and the third active region is formed in a third p-type well -; A step of forming a first via rail and a second via rail, respectively, on the first contact rail and the second contact rail; and A step of forming a third via rail on the above-mentioned cutting feature; A method including
10. As a semiconductor structure: A functional cell region including an n-type functional transistor and a p-type functional transistor; A first power transmission cell area including a first cutting feature and a first contact rail within the first cutting feature; A first power rail electrically connected to the source terminal of the above p-type functional transistor and the first contact rail of the above first power transmission cell region; A second power transmission cell region adjacent to the first power transmission cell region and comprising a second cutting feature and a second contact rail within the second cutting feature; and An insulating strip extending in a first direction from the first cutting feature to the second cutting feature. A semiconductor structure including

Description

Semiconductor Structure and Method for Forming the Same Claim of priority This application claims the benefit of U.S. Provisional Application No. 63/504,585, filed on May 26, 2023, under the title “Semiconductor structure and method of forming the same” and incorporated by reference herein. background The electronics industry is experiencing a continuing increase in demand for smaller and faster electronic devices capable of simultaneously supporting more complex and sophisticated functions. Consequently, the semiconductor industry continues the trend of manufacturing low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have largely been achieved by reducing semiconductor IC dimensions (e.g., minimum feature size) to improve production efficiency and lower associated costs. However, this size reduction has introduced greater complexity to the semiconductor manufacturing process. Therefore, the realization of continuous advancements in semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and technologies. Recently, multi-gate devices are being introduced to improve gate control by increasing gate-channel coupling, reduce off-state current, and mitigate single-channel effects (SCE). One such multi-gate device is the Gate-All-Around Transistor (GAA). GAA devices derive their name from their gate structure, which extends around the channel region to allow access to the channel from two or four sides. GAA devices are compatible with existing Complementary Metal-Oxide-Semiconductor (CMOS) processes and, due to their structure, can be actively scaled down while maintaining gate control and mitigating SCE. In conventional processes, GAA devices provide channels on silicon nanowires. However, integrating the fabrication of GAA features around nanowires can be a challenging task. For example, while current methods are satisfactory in many aspects, they still require continuous improvement. Various aspects of the present disclosure are best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not depicted in proportion. In practice, the dimensions of various features may be increased or decreased at will for the sake of clarity of discussion. FIGS. 1a, FIGS. 1b, FIGS. 1c, FIGS. 1d, FIGS. 1e, FIGS. 1f, FIGS. 1g, FIGS. 1k, FIGS. 1l and FIGS. 1m are plan views (layouts) illustrating the formation of semiconductor structures at various intermediate stages according to some embodiments of the present disclosure. FIGS. 1aa, FIGS. 1ba, FIGS. 1ma, and FIGS. 1mb are perspective views illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure. FIG. 1. FIG. 1ab, FIG. 1ac, FIG. 1ad and FIG. 1ae are cross-sectional views of a semiconductor structure corresponding to lines Y1-Y1, X1-X1, X2-X2 and Y2-Y2 of FIG. 1a, according to some embodiments of the present disclosure. FIGS. 1bb, FIGS. 1bc, FIGS. 1bd, and FIGS. 1be are cross-sectional views of a semiconductor structure corresponding to lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 of FIG. 1b, according to some embodiments of the present disclosure. FIGS. 1ca, FIGS. 1cb, FIGS. 1cc, and FIGS. 1cd are cross-sectional views of a semiconductor structure corresponding to lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 of FIG. 1c, according to some embodiments of the present disclosure. FIGS. 1da, FIGS. 1db, FIGS. 1dc, and FIGS. 1dd are cross-sectional views of a semiconductor structure corresponding to lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 of FIG. 1d, according to some embodiments of the present disclosure. FIGS. 1ea and FIGS. 1eb are cross-sectional views of a semiconductor structure corresponding to lines Y1-Y1 and X1-X1 of FIG. 1e according to some embodiments of the present disclosure. FIGS. 1fa, FIGS. 1fb, FIGS. 1fc and FIGS. 1fd are cross-sectional views of a semiconductor structure corresponding to lines Y1-Y1, X1-X1, X2-X2 and Y2-Y2 of FIG. 1f, according to some embodiments of the present disclosure. FIG. 1ga, FIG. 1gb, FIG. 1gc and FIG. 1gd are cross-sectional views of a semiconductor structure corresponding to lines Y1-Y1, X1-X1, X2-X2 and Y2-Y2 of FIG. 1g according to some embodiments of the present disclosure. FIGS. 1ha and FIGS. 1hb are cross-sectional views of a semiconductor structure corresponding to lines Y1-Y1 and X1-X1 of FIG. 1g according to some embodiments of the present disclosure. FIGS. 1ia, FIGS. 1ib, FIGS. 1ic, and FIGS. 1id are cross-sectional views of a semiconductor structure corresponding to lines Y1-Y1, X1-X1, and X2-X2 of FIG. 1g according to some embodiments of the present disclosure. FIGS. 1ja, FIGS. 1jb, FIGS. 1jc, and FIGS. 1jd are cross-sectional views of a semiconductor structure corresponding to lines Y1-Y1, X1-X1, X2-X2, and Y2-Y2 of FIG. 1g, according to some embodi