KR-102962233-B1 - VERTICAL SELF ALIGNED GATE ALL AROUND TRANSISTOR

KR102962233B1KR 102962233 B1KR102962233 B1KR 102962233B1KR-102962233-B1

Abstract

A method for forming a vertical gate all-around transistor comprises the step of forming a semiconductor layer stack on a lower source/drain region. The semiconductor layer stack comprises a first layer, a second layer on the first layer, and a third layer on the second layer. The first layer and the third layer have substantially the same composition and are optionally etchable with respect to the second layer. The first and second layers may optionally be removed and replaced with an internal spacer. The second layer may optionally be removed and replaced with a gate electrode.

Inventors

후앙 유-수안
첸 호우-유
충 쳉-팅
차이 진

Assignees

타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드

Dates

Publication Date: 20260507
Application Date: 20231120
Priority Date: 20230502

Claims (10)

In terms of method, A step of forming a trench adjacent to the channel region of the first vertical transistor within a semiconductor layer stack above the lower source/drain region of the first vertical transistor, wherein the channel region extends vertically from the lower source/drain region; A step of exposing a portion of the channel region by selectively removing the first layer of the stack with respect to the second layer of the stack through the trench using a first etching process - the first layer is disposed on the second layer -; Instead of the first layer, a step of forming an upper internal spacer in contact with the channel region; A step of removing the second layer of the stack through the trench using a second etching process; A step of forming a gate metal instead of the above second layer; and A method comprising the step of forming an upper source/drain region of the first vertical transistor on the channel region and the upper internal spacer.
In paragraph 1, The first etching process above removes the third layer of the stack, and A method in which the second layer is located between the first layer and the third layer prior to the first etching process.
In paragraph 2, A method comprising the step of forming a lower internal spacer in contact with the channel region and the lower source/drain region, instead of the third layer.
In paragraph 3, A step of removing the gate metal from the trench using a third etching process; and A method comprising the step of filling the trench with a level-interval dielectric layer in contact with the remaining portion of the gate metal and the upper inner spacer and the lower inner spacer after the third etching process.
In terms of method, A step of forming a first channel region of the first vertical transistor that extends vertically from a first lower source/drain region of the first vertical transistor; A step of forming a first lower internal spacer in contact with the first channel region; In the same deposition process as the first lower internal spacer, a step of forming a first upper internal spacer on the first lower internal spacer so as to be in contact with the first channel region; After forming the first lower internal spacer and the first upper internal spacer, a step of forming a gate dielectric on the top of the first lower internal spacer, the sidewall of the first channel region between the first upper internal spacer and the first lower internal spacer, and the bottom of the first upper internal spacer; A step of depositing gate metal between the first upper inner spacer and the first lower inner spacer; and A method comprising the step of forming a first upper source/drain region of the first vertical transistor in contact with the top of the first channel region and the top of the first upper internal spacer.
In paragraph 5, A step of forming a second channel region of the second vertical transistor that extends vertically from a second lower source/drain region of the second vertical transistor; A step of forming a second lower internal spacer in contact with the second channel region; In the same deposition process as the second lower internal spacer, a step of forming a second upper internal spacer on the second lower internal spacer so as to be in contact with the second channel region; After forming the second lower internal spacer and the second upper internal spacer, the step of forming the gate dielectric on the top of the second lower internal spacer, the sidewall of the second channel region between the second upper internal spacer and the second lower internal spacer, and the bottom of the second upper internal spacer; A step of depositing the gate metal between the second upper inner spacer and the second lower inner spacer; and A method comprising the step of forming a second upper source/drain region of the second vertical transistor in contact with the upper end of the second channel region and the upper end of the second upper internal spacer.
In terms of the device, First vertical transistor - The first vertical transistor is: First lower source/drain area; A first channel region extending vertically from the first lower source/drain region; A first upper source/drain region on the first channel region; A first lower internal spacer in contact with the first channel region and the first lower source/drain region; and Includes a first gate electrode positioned on the first lower inner spacer and laterally surrounding the first channel region -; A shallow trench separation area in contact with the first lower source/drain area; A first interlevel dielectric layer extending vertically from the above shallow trench separation region and in contact with the sidewalls of the first gate electrode and the first lower inner spacer - the first gate electrode is formed within the first interlevel dielectric layer -; A second inter-level dielectric layer on the first inter-level dielectric layer; and A first source/drain metal formed within the second inter-level dielectric layer and on the first upper source/drain region Includes, A device in which the shallow trench separation region extends laterally beyond the first inter-level dielectric layer below the first lower internal spacer.
In Paragraph 7, It includes a second vertical transistor, The above second vertical transistor is: A second lower source/drain region in contact with the above-mentioned shallow trench separation region; A second channel region extending vertically from the second lower source/drain region; A second lower internal spacer in contact with the second channel region and the second lower source/drain region; and It includes a second gate electrode located between a second upper inner spacer and a second lower inner spacer, and A device wherein the first inter-level dielectric layer is in contact with the sidewalls of the second gate electrode and the second lower inner spacer, and is located between the first lower inner spacer and the second lower inner spacer and between the first gate electrode and the second gate electrode.
In Paragraph 7, A device in which the first lower internal spacer includes a void.
In Paragraph 7, A device in which the first gate electrode includes a void.

Description

Vertical Self-Aligned Gate All Around Transistor The semiconductor integrated circuit industry has grown exponentially. Technological advancements in integrated circuit materials and design have led to the creation of generations of integrated circuits, each featuring smaller and more complex circuits than the previous generation. Throughout the evolution of integrated circuits, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the minimum component (or line) that can be produced using a manufacturing process) has decreased. This scaling down process generally offers the benefits of increased production efficiency and lower associated costs. However, this scaling down has also increased the complexity of processing and manufacturing integrated circuits. The aspects of the present disclosure are best understood from the following detailed description when read together with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not depicted to scale. In practice, the dimensions of various features may be increased or decreased at will for clarity of description. FIGS. 1a to 2f are cross-sectional and plan views of an integrated circuit at various processing stages according to some embodiments. FIGS. 3a through 15 include cross-sectional and plan views of an integrated circuit including some variations of the integrated circuit illustrated in FIGS. 1a through 2e according to some embodiments. FIG. 16 is a flowchart of a method for manufacturing an integrated circuit according to some embodiments. FIG. 17 is a flowchart of a method for manufacturing an integrated circuit according to some embodiments. The following disclosure provides many different embodiments or examples for implementing various features of the provided invention. To simplify the disclosure, specific exemplary components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. Additionally, the disclosure may repeat reference numbers and/or letters in various examples. Such repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and/or configurations discussed. Additionally, spatial terms such as “immediately below,” “below,” “lower,” “above,” and “upper” may be used herein for convenience of description to describe the relationship between one element or feature and another element(s) or feature(s) as illustrated in the drawings. These spatial terms are intended to include various orientations of the device in use or operation, in addition to the orientations illustrated in the drawings. The device may be oriented in other ways (it may be rotated 90 degrees or in other directions), and accordingly, the spatial descriptors used herein may be interpreted in the same manner. Terms indicating relative degrees, such as "approximately" and "substantially," should be interpreted as having ordinary skill in this technical field in light of current technical norms. The present disclosure generally relates to semiconductor devices, and more specifically to field-effect transistors (FETs), such as planar FETs, three-dimensional FinFETs (FinFETs), or nanostructure devices. Examples of nanostructure devices include gate-all-around (GAA) devices, nanosheet FETs (NSFETs), nanowire FETs (NWFETs), etc. In advanced technology nodes, the spacing of active regions between nanostructure devices is generally uniform, the source/drain epitaxy structure is symmetric, and a metal gate surrounds four sides of the nanostructure (e.g., nanosheet). Due to larger metal gate end caps and increased source/drain epitaxy sizes, the gate-drain capacitance ("Cgd") increases. Embodiments of the present disclosure reduce the spacing of active regions and improve the scaling of integrated circuit cell dimensions. In some embodiments, a vertical nanostructure transistor is formed. The vertical nanostructure transistor may include a lower source/drain region, an upper source/drain region, and a semiconductor nanostructure channel region extending vertically from the upper source/drain region to the lower source/drain region. A gate electrode laterally surrounds the semiconductor nanostructure channel region. A process for forming the vertical nanostructure transistor may include the step of forming a stack of semiconductor layers having different material concentrations so that various layers of the semiconductor sta