KR-102962234-B1 - TRANSISTOR CONTACTS AND METHODS OF FORMING THEREOF

Abstract

The device includes a first transistor layer including a first gate electrode and a second transistor layer including a second gate electrode stacked with the first transistor layer. An intermetallic structure including a conductive line is disposed between the first transistor layer and the second transistor layer. A first gate contact extends along the sidewall of the first gate electrode from the upper surface of the first gate electrode to the conductive line (48G). A second gate contact extends along the sidewall of the second gate electrode from the upper surface of the second gate electrode to the conductive line. The first gate electrode is electrically connected to the second gate electrode by the first gate contact, the second gate contact, and the conductive line.

Inventors

• 호우 융-친
• 루 리-충
• 쳉 지안-팅
• 린 웨이-쳉
• 린 춘-옌
• 후앙 칭-유

Assignees

• 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드

Dates

Publication Date

20260507

Application Date

20240306

Priority Date

20230630

Claims (10)

1. In terms of the device, A first transistor layer including a first gate electrode; A second transistor layer including a second gate electrode; An intermetallic structure between the first transistor layer and the second transistor layer - the intermetallic structure includes a first conductive line - ; A first gate contact extending along the sidewall of the first gate electrode from the upper surface of the first gate electrode to the first conductive line; and A second gate contact extending along the sidewall of the second gate electrode from the upper surface of the second gate electrode to the first conductive line Includes, A device in which the first gate electrode is electrically connected to the second gate electrode by the first gate contact, the second gate contact, and the first conductive line.
2. In claim 1, A device in which the first gate contact and the second gate contact each comprise tungsten (W), cobalt (Co), or ruthenium (Ru).
3. In claim 1, A device wherein the first conductive line is disposed in a dielectric layer, the first transistor layer further comprises a third gate electrode, and the device further comprises a third gate contact extending along the sidewall of the third gate electrode from the upper surface of the third gate electrode to the dielectric layer.
4. In claim 3, A device in which the dielectric layer covers the entire lateral surface of the third gate contact.
5. In claim 1, The first transistor layer further includes a first source/drain region, the second transistor layer further includes a second source/drain region, the intermetallic structure includes a second conductive line, and the device is: A first source/drain contact extending to the second conductive line through the first source/drain region; and A second source/drain contact extending to the second conductive line through the second source/drain region Includes more, A device in which the first source/drain region is electrically connected to the second source/drain region by the first source/drain contact, the second conductive line, and the second source/drain contact.
6. In claim 1, The above intermetallic structure is: Dielectric layer - the first conductive line is disposed in the dielectric layer - ; A first etching stop layer - the first gate contact extends through the first etching stop layer - ; and Second etching stop layer - The second gate contact extends through the second etching stop layer - Includes, A device in which the dielectric layer is disposed between the first etching stop layer and the second etching stop layer.
7. In claim 1, A device comprising a first bonding layer directly bonded to a second bonding layer by dielectric-dielectric bonding, wherein the first bonding layer and the second bonding layer are disposed between the first transistor layer and the intermetallic structure.
8. In terms of the device, First source/drain region in the first transistor layer; A first conductive line in a dielectric layer above the first source/drain region; A second source/drain region on the first conductive line - the second source/drain region is disposed on the second transistor layer - ; A first source/drain contact extending through the first source/drain region and contacting the first conductive line; A second source/drain contact extending through the second source/drain region and contacting the first conductive line; A third source/drain contact electrically connected to the first source/drain region - the first source/drain contact extends through the third source/drain contact - ; and A fourth source/drain contact electrically connected to the second source/drain region - the second source/drain contact extends through the fourth source/drain contact - Includes, A device in which the first source/drain region is electrically connected to the second source/drain region by the first source/drain contact, the second source/drain contact, the third source/drain contact, the fourth source/drain contact, and the first conductive line.
9. In claim 8, A device in which the first source/drain contact has a material composition different from the third source/drain contact, and the second source/drain contact has a material composition different from the fourth source/drain contact.
10. In terms of method, Step of patterning a first mask on a first gate electrode - said first gate electrode is placed on a first transistor layer - ; A step of patterning a first opening using the first mask as a patterning mask - the first opening exposes a first conductive line below the first gate electrode, and the step of patterning the first opening includes a step of etching the first gate electrode - ; A step of forming a first gate contact at the first opening that is electrically connected to the first conductive line; Step of patterning a second mask on a second gate electrode - said second gate electrode is placed on a second transistor layer - ; A step of patterning a second opening using the second mask as a patterning mask - the second opening exposes the first conductive line, and the step of patterning the second opening includes a step of etching the second gate electrode - ; and A step of forming a second gate contact at the second opening that is electrically connected to the first conductive line. A method including

Description

Transistor contacts and methods of forming thereof Priority Claims and Cross-references This application claims priority to U.S. Provisional Application No. 63/488,999 filed March 8, 2023, which is incorporated herein by reference. Semiconductor devices are used in various electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Typically, semiconductor devices are manufactured by sequentially depositing an insulating or dielectric material layer, a conductive material layer, and a semiconducting material layer on a semiconductor substrate, and then patterning the various material layers using lithography to form circuit components and elements. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) through a continuous reduction in the minimum feature size, which enables more components to be integrated within a given area. However, as the minimum feature size decreases, additional problems arise that must be addressed. The aspects of the present disclosure are best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practices, various features are not depicted to their actual scale. In fact, the dimensions of various features may be increased or decreased at will to clarify the description. Fig. 1, Fig. 2a, Fig. 2b, Fig. 3, Fig. 4a, Fig. 4b, Fig. 5, Fig. 6, Fig. 7a, Fig. 7b, Fig. 7c, Fig. 8a, Fig. 8b, Fig. 9a, Fig. 9b, Fig. 9c, Fig. 10a, Fig. 10b, Fig. 10c, Fig. 11a, Fig. 11b, Fig. 12a, Fig. 12b, Fig. 13a, Fig. 13b, Fig. 13c, Fig. 14a, Fig. 14b, Fig. 14c, Fig. 15a, Fig. 15b, Fig. 15c, Fig. 16a, Fig. 16b, Fig. 16c, Fig. 17a, Fig. 17b, Fig. 17c, Fig. 18a, Fig. 18b, Fig. 18c, Fig. 19a, Fig. 19b, Fig. 20, Fig. 21a, Fig. 21b, Fig. 22a, Fig. 22b, Fig. 22c, Fig. 22d, Fig. 22e, Fig. 22f, Fig. 23a, Fig. 23b, Fig. 23c, Fig. 23d, Fig. 23e, Fig. 23f, Fig. 24a, Fig. 24b, Fig. 24c, Fig. 25a, Fig. 25b, Fig. 25c, Fig. 26a, Fig. 26b, Fig. 26c, Fig. 27a, Fig. 27b, Fig. 27c, Fig. 28a, Fig. 28b, Fig. 28c, Fig. 29a, Fig. 29b, Fig. 30a, Fig. 30b, Fig. 30c, Fig. 31a, Fig. 31b, Fig. 31c, Fig. 32a, Fig. 32b, Fig. 32c, Fig. 33a, Fig. 33b, Fig. 34, Fig. 35a, Fig. 35b, Fig. 36a, Fig. 36b, Fig. 36c, Fig. 36d, Fig. 36e, Fig. 36f, Fig. 37a, Fig. 37b, Fig. 37c, Fig. 37d, Fig. 37e, Fig. 37f, Fig. 38a, Fig. 38b, Fig. 38c, Fig. 39a, Fig. 39b, Fig. 40a, Fig. 40b, Fig. 40c, Fig. 40d, Fig. 40e, Fig. 41a, Fig. 41b, Fig. 41c, Fig. 42a, Fig. 42b, Fig. 42c, Fig. 43a, Fig. 43b, Fig. 43c, Fig. 44a, Fig. 44b, Fig. 45a, Fig. 45b, Fig. 45c, Fig. 45d, Fig. FIGS. 45e, FIGS. 46a, FIGS. 46b, and FIGS. 46c illustrate various drawings of intermediate steps for manufacturing a CFET device according to some embodiments. FIGS. 47a, FIGS. 47b, and FIGS. 47c illustrate cross-sectional views of a CFET device according to some embodiments. FIGS. 48, FIGS. 49a, FIGS. 49b, FIGS. 49c, FIGS. 49d, FIGS. 49e and FIGS. 49f illustrate various drawings of intermediate steps for manufacturing a CFET device according to some embodiments. FIGS. 50a, FIGS. 50b, FIGS. 50c, FIGS. 51a, FIGS. 51b, FIGS. 51c, FIGS. 52a, FIGS. 52b, FIGS. 52c, FIGS. 53a, FIGS. 53b, FIGS. 53c, FIGS. 54a, FIGS. 54b, FIGS. 54c, FIGS. 55a, FIGS. 55b, FIGS. 55c, FIGS. 56a, FIGS. 56b, FIGS. 57, FIGS. 58a, FIGS. 58b, FIGS. 58c, FIGS. 59a, FIGS. 59b, FIGS. 59c, FIGS. 60a, FIGS. 60b, FIGS. 60c, FIGS. 61a, FIGS. 61b, FIGS. 62, FIGS. 63a, FIGS. 63b, and FIGS. 63c illustrate various drawings of intermediate steps for manufacturing a CFET device according to some embodiments. FIGS. 64a, FIGS. 64b, FIGS. 64c and FIGS. 64d illustrate top-down drawings and circuits of a CFET device according to some embodiments. The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and configurations are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features so that the first and second features do not come into direct contact. Additionally, the present disclosure may repeat reference numbers and/or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and/or configurations described. Additionally, spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to facilitate explanation and to describe the relationship between one comp