KR-102962238-B1 - METHODS OF FORMING BONDING STRUCTURES

KR102962238B1KR 102962238 B1KR102962238 B1KR 102962238B1KR-102962238-B1

Abstract

The method comprises forming a conductive pad on a substrate, forming a multilayer passivation structure on the conductive pad, patterning an upper portion of the multilayer passivation structure to form a first opening, forming a mask film on the sidewall surface of the patterned upper portion of the multilayer passivation structure, after forming the mask film, performing a first etching process to remove a portion of the multilayer passivation structure immediately below the first opening to form a second opening, after performing the first etching process, selectively removing the mask film, performing a second etching process to remove a portion of the multilayer passivation structure immediately below the second opening, thereby forming a third opening that exposes the conductive pad, and forming a bonding structure within the third opening, wherein the etchant of the second etching process is different from the etchant of the first etching process.

Inventors

황 싱-유안
리 친-쑤
호 이 첸

Assignees

타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드

Dates

Publication Date: 20260507
Application Date: 20231128
Priority Date: 20230508

Claims (10)

As a method, A step of forming a first dielectric structure on a conductive pad; A step of depositing a first etching stop layer on the first dielectric structure; A step of forming a second dielectric structure on the first etching stop layer; A step of depositing a second etching stop layer on the second dielectric structure; A step of forming a third dielectric structure on the second etching stop layer; A step of performing a first etching process to form a first opening that extends through the third dielectric structure and exposes the second etching stop layer; A step of forming a mask film extending along the sidewall of the third dielectric structure exposed by the first opening; A step of performing a second etching process that vertically extends the first opening to expose the first etching stop layer; A step of selectively removing the above mask film; A step of performing a third etching process that further extends the first opening vertically to expose the conductive pad; and Step of forming a conductive bonding structure within the further extended first opening A method including
In paragraph 1, The step of forming the first genome structure is: A step of forming an anti-reflective layer on the upper surface of the conductive pad; and A step of conformally depositing an oxide layer on the anti-reflective layer - a portion of the oxide layer is in direct contact with the sidewall surface of the conductive pad - ; A method that includes
In paragraph 1, A method in which the etchant of the third etching process comprises a mixture of CF4 and C4F8 .
In paragraph 3, A method in which the ratio of the volume of CF4 to the volume of C4F8 is greater than 2.
In paragraph 3, A method in which the etchant of the first etching process is different from the etchant of the third etching process.
In paragraph 1, A method wherein the step of forming the mask film is performed prior to the step of performing the second etching process, and the step of selectively removing the mask film is performed prior to the step of performing the third etching process.
In claim 1, the step of forming the second genome structure is: A step of forming an oxide liner interposed between a first oxide layer and a second oxide layer; A step of forming a third etching stop layer on the oxide liner and on the second oxide layer; and Step of forming a third oxide layer on the third etching stop layer A method that includes
In paragraph 1, A method in which, in a cross-sectional view, the shape of the bonding structure includes a funnel shape.
As a method, A step of providing a workpiece including a conductive pad formed on a substrate; A step of forming a multilayer passivation structure on the conductive pad; A step of patterning the upper portion of the multilayer passivation structure to form a first opening; A step of forming a mask film on the sidewall surface of the patterned upper portion of the multilayer passivation structure; After the step of forming the mask film, a step of performing a first etching process to remove a portion of the multilayer passivation structure located immediately below the first opening in order to form a second opening; After the step of performing the first etching process, a step of selectively removing the mask film; A step of performing a second etching process to remove a portion of the multilayer passivation structure located immediately below the second opening, thereby forming a third opening that exposes the conductive pad - the etchant of the second etching process is different from the etchant of the first etching process - ; and Step of forming a conductive bonding structure within the third opening A method including
As a semiconductor structure: A conductive pad formed on a substrate; A multilayer passivation structure on the conductive pad above - the multilayer passivation structure comprises a dielectric film, and the ratio of the atomic percentage of silicon to the atomic percentage of oxygen is between 0.3 and 0.5 - ; and A bonding structure extending through the above-described multilayer passivation structure and electrically coupled to the above-described conductive pad, comprising a first portion and a second portion above the first portion - in the cross-sectional view, the shape of the bonding structure includes a funnel shape - ; Includes, The first width of the first part of the bonding structure is smaller than the second width of the second part of the bonding structure, and A semiconductor structure in which the sidewall of the bonding structure includes a kink at the boundary between the first part and the second part.

Description

Methods of Forming Bonding Structures [Cross-references to related technologies] This application claims the benefit of U.S. provisional application No. 63/387,603 filed on December 15, 2022, the entirety of said provisional application is incorporated herein by reference. The semiconductor integrated circuit (IC) industry has undergone exponential growth. Technological advancements in IC materials and design have enabled the production of multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout the evolution of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometric size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. However, this miniaturization has also increased the complexity of fabricating and manufacturing ICs. For example, as more device dies are packaged within the same package to achieve greater functionality, integrated circuit packages are becoming increasingly complex. System-on-integrated-chip (SoIC) has been developed to include multiple device dies, such as processors and memory cubes, within the same package. An SoIC may include device dies formed using different technologies and have different functional units bonded to the same device dies, thereby forming a system. This can reduce manufacturing costs and optimize device performance. Conductive pads and bonding structures (e.g., bonding pad vias (BPVs) and bonding pad metal lines (BPMs)) are formed within the device dies, making it possible for the SoIC to meet satisfactory electrical functions. While conventional techniques for forming bonding structures are generally suitable, they are not satisfactory in all aspects. The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard industry practice, various features are not depicted to actual scale and are used for illustrative purposes only. In practice, the dimensions of various features may be increased or decreased at will for clarity of description. FIG. 1 illustrates a flowchart of a method for forming a semiconductor structure according to some embodiments of the present disclosure. FIGS. 2, FIGS. 3, FIGS. 4, FIGS. 5, FIGS. 6, FIGS. 7, FIGS. 8, FIGS. 9, FIGS. 10, FIGS. 11, FIGS. 12, FIGS. 13, FIGS. 14, FIGS. 15, FIGS. 16, FIGS. 17, FIGS. 18, FIGS. 19 and FIGS. 20 illustrate partial cross-sectional views of a semiconductor structure during a fabrication process according to the method of FIG. 1, according to various embodiments of the present disclosure. The following disclosure provides a number of different embodiments or examples for implementing different features of the provided subject matter. To simplify the disclosure, specific examples of components and arrangements are described below. These are, of course, examples only and are not intended to be limiting. For example, in the detailed description below, the formation of a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, or an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. Additionally, the disclosure may repeat reference numerals and/or letters in various examples. Such repetition is for simplicity and clarity and does not indicate the relationship between the various embodiments and/or configurations described by themselves. In this specification, spatially relative terms such as “below,” “below,” “lower,” “above,” “upper,” etc. may be used for convenience of description to explain the relationship of one element or feature to another element(s) or feature(s) as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations illustrated in the drawings. The device may be oriented differently (rotated 90 degrees or oriented in a different way), and the spatially relative terms used in this specification may likewise be interpreted accordingly. Additionally, when a number or a range of numbers is described as “about,” “approximately,” etc., the term is intended to include a number within a reasonable range, taking into account variations that inevitably occur during fabrication, as understood by those skilled in the art. For example, a number or a range of numbers includes a reasonable range that includes the described number, such as within +/- 10% of the described number, based on known fabrication tolerances related to fabricating a feature having ch