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KR-102962383-B1 - Memristor device, method of fabricating the same, synaptic device including the same and neuromorphic device including a synaptic device

KR102962383B1KR 102962383 B1KR102962383 B1KR 102962383B1KR-102962383-B1

Abstract

A memristor device, a method for manufacturing the same, a synaptic device including a memristor device, and a neuromorphic device including a synaptic device are disclosed. The disclosed memristor device may comprise a first electrode corresponding to an inactive electrode, a second electrode corresponding to an active electrode disposed spaced apart from the first electrode, a resistance change layer comprising a polymer disposed between the first electrode and the second electrode, and an insertion layer comprising an oxide disposed between the first electrode and the resistance change layer. An electrochemical metallization mechanism (ECM) filament may be formed within the resistance change layer, and a valence change mechanism (VCM) filament may be formed within the insertion layer. The memristor device may have synaptic characteristics according to a change in resistance of the resistance change layer. The insertion layer may be an Al₂O₃ layer . The insertion layer may be an Al₂O₃ layer formed by an atomic layer deposition (ALD) process using a process temperature of about 200°C or higher.

Inventors

  • 박상수
  • 최성율
  • 차준회
  • 오정엽

Assignees

  • 에스케이하이닉스 주식회사
  • 한국과학기술원

Dates

Publication Date
20260507
Application Date
20220323

Claims (19)

  1. A first electrode corresponding to an inert electrode; A second electrode corresponding to an active electrode, positioned spaced apart from the first electrode; A resistance changing layer comprising a polymer disposed between the first electrode and the second electrode; and It is disposed between the first electrode and the resistance change layer and comprises an insertion layer including an oxide, and An ECM (electrochemical metallization mechanism) filament is formed within the resistance change layer, and an oxygen vacancy-based VCM (valence change mechanism) filament is formed within the insertion layer by causing a hard breakdown due to a voltage applied between the first electrode and the second electrode. The above VCM filament is a memristor device that reduces the randomness of the formation and collapse of the ECM filament by inducing the formation location and conduction path of the ECM filament within the resistance change layer.
  2. In Article 1, The above insertion layer is a memristor element in which the Al₂O₃ layer is inserted.
  3. In Article 1, The above-mentioned insertion layer is a memristor device in which the insertion layer is an Al₂O₃ layer formed by an ALD (atomic layer deposition) process using a process temperature of 200°C or higher.
  4. In Article 1, The above insertion layer is a memristor device having a thickness of 1 nm to 50 nm.
  5. In Article 1, The above polymer is a memristor device comprising V3D3(1,3,5-trivinyl-1,3,5-trimethylcyclotrisiloxane).
  6. In Article 1, The above resistance change layer is a memristor device having a thickness of 5 nm to 100 nm.
  7. In Article 1, The above resistance change layer is a single membrane composed of the above polymer, and The above insertion layer is a single film composed of the oxide, and A first surface of the insertion layer is in contact with the first electrode, and a second surface facing the first surface of the insertion layer is in contact with the resistance changing layer. A memristor element in which a first surface of the resistance changing layer is in contact with the insertion layer, and a second surface facing the first surface of the resistance changing layer is in contact with the second electrode.
  8. In Article 1, The first electrode above is a memristor element comprising at least one of Pt and Al.
  9. In Article 1, The second electrode above is a memristor element comprising at least one of Cu, Ag, and Ni.
  10. In Article 1, A memristor device configured such that the potentialization of the memristor device by the gradual increase in the conductivity of the resistance change layer is performed in a current sweep manner.
  11. A step of forming a first electrode corresponding to an inert electrode; A step of forming an insertion layer containing an oxide on the first electrode; A step of forming a resistance change layer containing a polymer on the above insertion layer; and The method includes the step of forming a second electrode corresponding to an active electrode on the resistance change layer, and A method for manufacturing a memristor device having synaptic characteristics according to a change in resistance of the resistance change layer, wherein an electrochemical metallization mechanism (ECM) filament is formed within the resistance change layer, and an oxygen vacancy-based valence change mechanism (VCM) filament is formed within the insertion layer by causing a hard breakdown by a voltage applied between the first electrode and the second electrode, and the VCM filament reduces the randomness of the formation and breakdown of the ECM filament by inducing the formation location and conduction path of the ECM filament within the resistance change layer.
  12. In Article 11, A method for manufacturing a memristor device in which the above-mentioned insertion layer is an Al₂O₃ layer.
  13. In Article 11, A method for manufacturing a memristor device in which the above-mentioned insertion layer is an Al₂O₃ layer formed by an atomic layer deposition (ALD) process using a process temperature of 200°C or higher.
  14. In Article 11, A method for manufacturing a memristor device in which the above-mentioned insertion layer has a thickness of 1 nm to 50 nm.
  15. In Article 11, A method for manufacturing a memristor device comprising the above polymer V3D3(1,3,5-trivinyl-1,3,5-trimethylcyclotrisiloxane).
  16. In Article 11, A method for manufacturing a memristor device in which the resistance change layer is formed by an iCVD (initiated chemical vapor deposition) process.
  17. In Article 11, A method for manufacturing a memristor device having a resistance change layer with a thickness of 5 to 100 nm.
  18. A synaptic device comprising a memristor element as described in claim 1.
  19. A neuromorphic device comprising a synaptic element as described in claim 18.

Description

Memristor device, method of fabricating the same, synaptic device including the same and neuromorphic device including a synaptic device The present invention relates to electronic devices and applications thereof, and more specifically, to a memristor device and a method for manufacturing the same, a synaptic device including a memristor device and a neuromorphic device including a synaptic device. The rapid advancement of software and hardware has led to the emergence of artificial intelligence (AI) technologies, such as real-time video analysis and language translation. However, existing artificial neural networks based on GPUs (Graphic Processing Units) utilize the Von Neumann architecture, where memory and processors are separated, resulting in inefficiency in terms of energy consumption. Consequently, software-based AI neural network systems utilizing cloud servers are being employed instead of performing AI-based algorithm computations directly on portable devices. Since the use of cloud servers entails significant latency and security issues, there is a demand for alternative technologies that can implement artificial neural networks directly on portable devices. Accordingly, active research is underway to move away from the Von Neumann architecture and realize biomimetic computing by utilizing analog memory devices. A memristor is a compound word of memory and resistance, and it is a two-terminal device whose resistance state changes in response to external electrical stimulation. In particular, memristors have been extensively studied for high-density memory applications due to their simple structure. Furthermore, by enhancing analog operating characteristics, memristors can simultaneously implement memory and computation functions and mimic the role of synapses in the brain. Memristors are broadly classified into two types: one is an oxide-based RAM (OxRAM) in which a conducting path is formed by oxygen vacancies in a metal oxide film, and the other is a conductive bridge RAM (CBRAM) in which a conducting path is formed by the penetration of metal ions into an electrolyte. CBRAM has advantages such as fast operating speed, high miniaturization potential, freedom in medium selection, and a high ON/OFF ratio. However, CBRAM has a disadvantage in that it is difficult to implement reliable analog switching-based characteristics because, when the conducting filament connecting the bottom electrode and the top electrode comes into contact with the electrode, it is difficult to implement the gradual collapse of the conducting filament due to strong interactions between metals within the filament. In addition, there is a problem in that it is difficult to implement switching characteristics with excellent reliability due to the randomness (irregularity) of the generation and collapse of the conducting filament. Most existing research on CBRAM-based memristor synapse devices has focused on the linear update (increase) of conductivity based on in-situ training methods, while technological development to improve or secure the reliability (long-term state reliability) of the synaptic device's conductivity values has been insufficient. Furthermore, according to recent reports, CBRAM is being discussed as a synapse device that can be better optimized for ex-situ training. Therefore, there is a need for the development of CBRAM memristor devices that possess linear conductivity update characteristics, the ability to reach a desired target conductivity value, and enhanced long-term state reliability. FIG. 1 is a cross-sectional view showing a memristor element according to one embodiment of the present invention. FIG. 2 is a graph showing the results of evaluating the potentialization-depression characteristics of a memristor device according to one embodiment of the present invention. FIG. 3 is a graph showing the retention characteristics of the conductivity value of a memristor device according to one embodiment of the present invention over time. FIGS. 4a to 4e are cross-sectional views showing a method for manufacturing a memristor device according to one embodiment of the present invention. FIG. 5 is a graph showing the change in resistance (Ω) according to an increase in temperature (K) of a memristor element according to one embodiment of the present invention. Figure 6 is a graph showing the relationship between the TT 0 value and the (R/R 0 )-1 value, obtained from the results of Figure 5. Figure 7 is a graph showing the change in the resistance temperature coefficient (α R ) according to the diameter of the Cu nanowire. FIG. 8 is a cross-sectional view schematically showing the configuration of a memristor element according to one embodiment of the present invention. FIG. 9 is a graph showing a current pulse applied to a memristor element according to an embodiment of the present invention, and the change in conductivity and applied voltage accordingly. Figure 10 is a graph showing the current pulse a