KR-102962385-B1 - MEMORY CIRCUIT, RESISTIVE NON-VOLATILE MEMORY AND OPERATION METHOD THEREOF

Abstract

The present invention provides a resistive non-volatile memory comprising at least one gate-resistance-variable field-effect transistor and a unipolar source/channel/drain diode. The at least one gate-resistance-variable field-effect transistor is electrically connected to at least one bit line. The unipolar source/channel/drain diode is implemented by a field-effect transistor without a gate electrode. Two terminals of the unipolar source/channel/drain diode are electrically connected to a source line and at least one gate-resistance-variable field-effect transistor.

Inventors

• 쉬에, 이 레이
• 청, 유안 헹

Assignees

• 이레이트로닉스 컴퍼니 리미티드

Dates

Publication Date

20260507

Application Date

20241224

Priority Date

20240805

Claims (19)

1. As a resistive non-volatile memory, At least one gate-resistively-changeable field effect transistor electrically connected to at least one bit line; and Unipolar source/channel/drain diode implemented by a field-effect transistor without a gate electrode Includes, The two terminals of the above-mentioned unipolar source/channel/drain diode are each electrically connected to a source line and at least one gate-resistance-variable field-effect transistor, and The gate of the at least one gate-resistance-variable field-effect transistor is electrically connected to the at least one bit line, the first terminal of the at least one gate-resistance-variable field-effect transistor is floating, the two terminals of the unipolar source/channel/drain diode are electrically connected to the source line and the second terminal of the at least one gate-resistance-variable field-effect transistor, and the unipolar source/channel/drain diode is an npn diode or a nin diode. The above-described unipolar source/channel/drain diode comprises: a floating dummy gate; and a first source/drain diffusion region and a second source/drain diffusion region disposed on opposite sides of the floating dummy gate. Resistant non-volatile memory.
2. In paragraph 1, The first source/drain diffusion region contacts one terminal of a contact plug, and the other terminal of the contact plug contacts the source line. Resistant non-volatile memory.
3. In paragraph 2, The above unipolar source/channel/drain diode and the at least one gate-resistance-variable field-effect transistor share the second source/drain diffusion region, and The above at least one gate-resistance-changeable field-effect transistor is: A shallow trench isolation in direct contact with the gate of at least one gate-resistance-variable field-effect transistor Includes, The shallow trench isolation portion and the second source/drain diffusion region are each disposed on opposite sides of the gate of the at least one gate-resistance-variable field-effect transistor, the shallow trench isolation portion acts as the first terminal of the at least one gate-resistance-variable field-effect transistor, and the second source/drain diffusion region acts as the second terminal of the at least one gate-resistance-variable field-effect transistor. Resistant non-volatile memory.
4. As a resistive non-volatile memory, At least one gate-resistively-changeable field effect transistor electrically connected to at least one bit line; and Unipolar source/channel/drain diode implemented by a field-effect transistor without a gate electrode Includes, The two terminals of the above-mentioned unipolar source/channel/drain diode are each electrically connected to a source line and at least one gate-resistance-variable field-effect transistor, and The two terminals of the above-mentioned unipolar source/channel/drain diode are each electrically connected to the source line and the gate of the at least one gate-resistance-variable field-effect transistor, the first terminal of the at least one gate-resistance-variable field-effect transistor is floating, and the second terminal of the at least one gate-resistance-variable field-effect transistor is electrically connected to the at least one bit line, and the unipolar source/channel/drain diode is a pnp diode or a pip diode. The above-described unipolar source/channel/drain diode comprises: a floating dummy gate; and a first source/drain diffusion region and a second source/drain diffusion region disposed on opposite sides of the floating dummy gate. Resistant non-volatile memory.
5. In paragraph 4, A first conductive layer and a second conductive layer electrically insulated from each other; A first contact plug having two terminals each in contact with the first source/drain diffusion region and the first conductive layer; A second contact plug having two terminals that respectively contact the first conductive layer and the source line; A third contact plug having two terminals each in contact with the second source/drain diffusion region and the second conductive layer; and A fourth contact plug having two terminals each in contact with the gate and the second conductive layer of the at least one gate-resistance-variable field-effect transistor. including more Resistant non-volatile memory.
6. In paragraph 5, The above at least one gate-resistance-changeable field-effect transistor is: A shallow trench isolation portion in direct contact with the gate of the at least one gate-resistance-variable field-effect transistor — the shallow trench isolation portion serves as the first terminal of the at least one gate-resistance-variable field-effect transistor —; and A third source/drain diffusion region disposed on opposite sides of the gate of the at least one gate-resistance-variable field-effect transistor and the shallow trench isolation portion — the third source/drain diffusion region serves as the second terminal of the at least one gate-resistance-variable field-effect transistor — including Resistant non-volatile memory.
7. In paragraph 6, A fifth contact plug having two terminals each contacting the third source/drain diffusion region and the at least one bit line. including more Resistant non-volatile memory.
8. As a memory circuit, Multiple memory units arranged in an array Includes, Each of the above memory units includes a resistive non-volatile memory, and The above resistive non-volatile memory is: At least one gate-resistance-variable field-effect transistor electrically connected to at least one bit line; and Unipolar source/channel/drain diode implemented by a field-effect transistor without a gate electrode Includes, The two terminals of the above-mentioned unipolar source/channel/drain diode are each electrically connected to a source line and at least one gate-resistance-variable field-effect transistor, and The gate of the at least one gate-resistance-variable field-effect transistor is electrically connected to the at least one bit line, the first terminal of the at least one gate-resistance-variable field-effect transistor is floating, the two terminals of the unipolar source/channel/drain diode are electrically connected to the source line and the second terminal of the at least one gate-resistance-variable field-effect transistor, and the unipolar source/channel/drain diode is an npn diode or a nin diode. The above-described unipolar source/channel/drain diode comprises: a floating dummy gate; and a first source/drain diffusion region and a second source/drain diffusion region disposed on opposite sides of the floating dummy gate. Memory circuit.
9. In paragraph 8, Each of the above memory units includes another resistive non-volatile memory, and One terminal of the other resistive nonvolatile memory is electrically connected to the resistive nonvolatile memory and the at least one bit line, and The other terminal of the aforementioned resistive non-volatile memory is electrically connected to another source line. Memory circuit.
10. In paragraph 8, Each of the above memory units includes another resistive non-volatile memory, and One terminal of the other resistive nonvolatile memory is electrically connected to the resistive nonvolatile memory and the source line, and The other terminal of the other resistive non-volatile memory is electrically connected to the at least one bit line. Memory circuit.
11. In paragraph 8, Each of the above memory units includes another resistive non-volatile memory, and The aforementioned other resistive non-volatile memory is: At least another gate-resistance-variable field-effect transistor having a gate electrically connected to at least one other bit line — the first terminal of the at least another gate-resistance-variable field-effect transistor is floating —; and Another unipolar source/channel/drain diode implemented by another field-effect transistor without a gate electrode — the two terminals of said another unipolar source/channel/drain diode are each electrically connected to said source line and the second terminal of said at least another gate-resistance-variable field-effect transistor — including Memory circuit.
12. As a memory circuit, Multiple memory units arranged in an array Includes, Each of the above memory units includes a resistive non-volatile memory, and The above resistive non-volatile memory is: At least one gate-resistance-variable field-effect transistor electrically connected to at least one bit line; and Unipolar source/channel/drain diode implemented by a field-effect transistor without a gate electrode Includes, The two terminals of the above-mentioned unipolar source/channel/drain diode are each electrically connected to a source line and at least one gate-resistance-variable field-effect transistor, and The two terminals of the above-mentioned unipolar source/channel/drain diode are electrically connected to the source line and the gate of the at least one gate-resistance-variable field-effect transistor, the first terminal of the at least one gate-resistance-variable field-effect transistor is floating, and the second terminal of the at least one gate-resistance-variable field-effect transistor is electrically connected to the at least one bit line. The above unipolar source/channel/drain diode is a pnp diode or a pip diode, and The above-described unipolar source/channel/drain diode comprises: a floating dummy gate; and a first source/drain diffusion region and a second source/drain diffusion region disposed on opposite sides of the floating dummy gate. Memory circuit.
13. In Paragraph 12, Each of the above memory units includes another resistive non-volatile memory, and The aforementioned other resistive non-volatile memory is: At least another gate-resistance-variable field-effect transistor having a floating first terminal — the second terminal of the at least another gate-resistance-variable field-effect transistor is electrically connected to the at least one bit line —; and Another unipolar source/channel/drain diode implemented by another field-effect transistor without a gate electrode — the two terminals of said another unipolar source/channel/drain diode are each electrically connected to another source line and the gate of said at least another gate-resistance-variable field-effect transistor — including Memory circuit.
14. As a method of operation of resistive non-volatile memory, The above resistive non-volatile memory comprises interconnected gate-resistive-changeable field-effect transistors and unipolar source/channel/drain diodes, and The above method of operation is: To operate the resistive non-volatile memory, a step of applying a zero voltage to one of a bit line and a source line, and applying a non-zero voltage to the other of the bit line and the source line. Includes, The gate-resistance-variable field-effect transistor is electrically connected to the bit line, the unipolar source/channel/drain diode is implemented by a field-effect transistor without a gate electrode, and the two terminals of the unipolar source/channel/drain diode are electrically connected to the source line and the gate-resistance-variable field-effect transistor, respectively. The gate of the gate-resistance-variable field-effect transistor is electrically connected to the bit line, the first terminal of the gate-resistance-variable field-effect transistor is floating, the two terminals of the unipolar source/channel/drain diode are electrically connected to the source line and the second terminal of the gate-resistance-variable field-effect transistor, and the unipolar source/channel/drain diode is an npn diode or a nin diode. The above-described unipolar source/channel/drain diode comprises: a floating dummy gate; and a first source/drain diffusion region and a second source/drain diffusion region disposed on opposite sides of the floating dummy gate. Method of operation of resistive non-volatile memory.
15. In Paragraph 14, The above method of operation is: In a forming process, when the resistive non-volatile memory is selected, a step of applying a forming voltage to the bit line and applying the zero voltage to the source line; In a setting process, when the resistive non-volatile memory is selected, a step of applying a setting voltage to the bit line and applying the zero voltage to the source line — the absolute value of the setting voltage is less than or equal to the absolute value of the forming voltage —; In a resetting process, when the resistive non-volatile memory is selected, a step of applying a reset voltage to the bit line and applying the zero voltage to the source line — the absolute value of the reset voltage is smaller than the absolute value of the set voltage —; and In a reading process, when the resistive non-volatile memory is selected, a step of applying a read voltage to the bit line and applying the zero voltage to the source line — the absolute value of the read voltage is smaller than the absolute value of the reset voltage — including Method of operation of resistive non-volatile memory.
16. In paragraph 15, In the above forming process, when the resistive non-volatile memory is not selected, a step of applying a voltage between 1/2 and 1/5 of the forming voltage to the source line and applying the zero voltage to the bit line; In the above setting process, when the resistive non-volatile memory is not selected, a step of applying a voltage between 1/2 and 1/5 of the setting voltage to the source line and applying the zero voltage to the bit line; In the above reset process, when the resistive non-volatile memory is not selected, a step of applying a voltage between 1/2 and 1/5 of the reset voltage to the source line and applying the zero voltage to the bit line; and In the above reading process, when the resistive non-volatile memory is not selected, a voltage between 1/2 and 1/5 of the reading voltage is applied to the source line, and the zero voltage is applied to the bit line. including more Method of operation of resistive non-volatile memory.
17. As a method of operation of resistive non-volatile memory, The above resistive non-volatile memory comprises interconnected gate-resistive-changeable field-effect transistors and unipolar source/channel/drain diodes, and The above method of operation is: To operate the resistive non-volatile memory, a step of applying a zero voltage to one of a bit line and a source line, and applying a non-zero voltage to the other of the bit line and the source line. Includes, The gate-resistance-variable field-effect transistor is electrically connected to the bit line, the unipolar source/channel/drain diode is implemented by a field-effect transistor without a gate electrode, and the two terminals of the unipolar source/channel/drain diode are electrically connected to the source line and the gate-resistance-variable field-effect transistor, respectively. The two terminals of the above-mentioned unipolar source/channel/drain diode are electrically connected to the source line and the gate of the above-mentioned gate-resistance-variable field-effect transistor, the first terminal of the above-mentioned gate-resistance-variable field-effect transistor is floating, the second terminal of the above-mentioned gate-resistance-variable field-effect transistor is electrically connected to the bit line, and the above-mentioned unipolar source/channel/drain diode is a pnp diode or a pip diode, and The above-described unipolar source/channel/drain diode comprises: a floating dummy gate; and a first source/drain diffusion region and a second source/drain diffusion region disposed on opposite sides of the floating dummy gate. Method of operation of resistive non-volatile memory.
18. In Paragraph 17, The above method of operation is: In a forming process, when the resistive non-volatile memory is selected, a step of applying a forming voltage to the source line and applying the zero voltage to the bit line; In the setting process, when the resistive non-volatile memory is selected, a step of applying a setting voltage to the source line and applying the zero voltage to the bit line — the absolute value of the setting voltage is less than or equal to the absolute value of the forming voltage —; In a reset process, when the resistive non-volatile memory is selected, a step of applying a reset voltage to the source line and applying the zero voltage to the bit line — the absolute value of the reset voltage is smaller than the absolute value of the set voltage —; and In a read process, when the resistive non-volatile memory is selected, a step of applying a read voltage to the source line and applying the zero voltage to the bit line — the absolute value of the read voltage is smaller than the absolute value of the reset voltage — including Method of operation of resistive non-volatile memory.
19. In Paragraph 18, In the above forming process, when the resistive non-volatile memory is not selected, a step of applying a voltage between 1/2 and 1/5 of the forming voltage to the bit line and applying the zero voltage to the source line; In the above setting process, when the resistive non-volatile memory is not selected, a step of applying a voltage between 1/2 and 1/5 of the setting voltage to the bit line and applying the zero voltage to the source line; In the above reset process, when the resistive non-volatile memory is not selected, a step of applying a voltage between 1/2 and 1/5 of the reset voltage to the bit line and applying the zero voltage to the source line; and In the above reading process, when the resistive non-volatile memory is not selected, a voltage between 1/2 and 1/5 of the reading voltage is applied to the bit line, and the zero voltage is applied to the source line. including more Method of operation of resistive non-volatile memory.

Description

Memory circuit, resistive non-volatile memory and method of operation thereof {MEMORY CIRCUIT, RESISTIVE NON-VOLATILE MEMORY AND OPERATION METHOD THEREOF} The present invention relates to storage circuits and operating methods, and more specifically, to a memory circuit, a resistive non-volatile memory and a method of operating the same. With the advancement of Moore's Law, various embedded memories have been mass-produced by foundries. In many application fields, semiconductor memory is widely used in various electronic products. Traditional embedded memories have been formed separately at the front-end-of-line (FEoL) and back-end-of-line (BEoL) of CMOS technology, which increases the number of lithographic masks and manufacturing steps, leading to cost constraints. Additionally, traditional embedded memory technologies use 3-terminal active devices as control transistors, which require additional word lines and associated peripheral circuits, resulting in increased power consumption and chip layout overhead. In one or more different aspects, the present invention relates to a memory circuit, a resistive nonvolatile memory, and a method of operating the same. One embodiment of the present invention relates to a resistive nonvolatile memory. The resistive nonvolatile memory comprises at least one gate-resistively-changeable field effect transistor and a unipolar source/channel/drain diode. The at least one gate-resistively-changeable field effect transistor is electrically connected to at least one bit line. The unipolar source/channel/drain diode is implemented by a field effect transistor without a gate electrode, and the two terminals of the unipolar source/channel/drain diode are electrically connected to a source line and at least one gate-resistively-changeable field effect transistor, respectively. In one embodiment of the present invention, the gate of at least one gate-resistance-variable field effect transistor is electrically connected to at least one bit line, the first terminal of at least one gate-resistance-variable field effect transistor is floating, and the two terminals of a unipolar source/channel/drain diode are electrically connected to the source line and the second terminal of at least one gate-resistance-variable field effect transistor, and the unipolar source/channel/drain diode is an npn diode or a nin diode. In one embodiment of the present invention, a unipolar source/channel/drain diode comprises a floating dummy gate, a first source/drain diffusion region, and a second source/drain diffusion region. The first source/drain diffusion region and the second source/drain diffusion region are disposed on opposite sides of the floating dummy gate, and the first source/drain diffusion region contacts one terminal of a contact plug, and the other terminal of the contact plug contacts a source line. In one embodiment of the present invention, a unipolar source/channel/drain diode and at least one gate-resistance-variable field-effect transistor share a second source/drain diffusion region, and at least one gate-resistance-variable field-effect transistor includes a shallow trench isolation. The shallow trench isolation is in direct contact with the gate of at least one gate-resistance-variable field-effect transistor, and the shallow trench isolation and the second source/drain diffusion region are each disposed on opposite sides of the gate of at least one gate-resistance-variable field-effect transistor, the shallow trench isolation acts as a first terminal of at least one gate-resistance-variable field-effect transistor, and the second source/drain diffusion region acts as a second terminal of at least one gate-resistance-variable field-effect transistor. In one embodiment of the present invention, two terminals of a unipolar source/channel/drain diode are each electrically connected to a source line and the gate of at least one gate-resistance-variable field-effect transistor, the first terminal of at least one gate-resistance-variable field-effect transistor is floating, and the second terminal of at least one gate-resistance-variable field-effect transistor is electrically connected to at least one bit line, and the unipolar source/channel/drain diode is a pnp diode or a pip diode. In one embodiment of the present invention, a unipolar source/channel/drain diode comprises a floating dummy gate, a first source/drain diffusion region, and a second source/drain diffusion region. The first source/drain diffusion region and the second source/drain diffusion region are disposed on opposite sides of the floating dummy gate. In one embodiment of the present invention, the resistive nonvolatile memory further comprises a first conductive layer, a second conductive layer, a first contact plug, a second contact plug, a third contact plug, and a fourth contact plug. The first conductive layer and the second conductive layer are electrically insulated from each other. The first contact plug h