KR-102962401-B1 - SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Abstract

Embodiments of the present invention can provide a semiconductor device and a method for manufacturing the same that can cover the entire surface of a dielectric layer by increasing continuity while maintaining the thickness of the upper electrode of a capacitor. Additionally, embodiments of the present invention can provide a semiconductor device and a method for manufacturing the same that can mitigate the bending phenomenon of a lower electrode. A semiconductor device according to the present embodiment may include a lower electrode structure on a substrate; a dielectric layer on the lower electrode structure; and an upper electrode structure on the dielectric layer that includes an amorphous layer containing silicon and in contact with the dielectric layer.

Inventors

• 안지훈
• 김병상
• 홍승범

Assignees

• 에스케이하이닉스 주식회사

Dates

Publication Date

20260511

Application Date

20211013

Claims (20)

1. Lower electrode structure on the upper part of the substrate; A dielectric layer on the lower electrode structure above; and The upper electrode structure comprises an amorphous layer containing silicon that is in contact with the dielectric layer on the dielectric layer, wherein The above upper electrode structure is, Amorphous titanium silicon nitride in direct contact with the dielectric layer on the dielectric layer above; and Crystalline titanium nitride in direct contact with the amorphous titanium silicon nitride on the amorphous titanium silicon nitride A semiconductor device including
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3. In paragraph 1, A semiconductor device in which the above amorphous titanium silicon nitride has continuity and covers the entire surface of the dielectric layer.
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6. In paragraph 1, A semiconductor device in which the thickness of the amorphous titanium silicon nitride is smaller than the thickness of the crystalline titanium nitride.
7. In paragraph 1, The above upper electrode structure is a semiconductor device further comprising a semiconductor material layer on the crystalline titanium nitride.
8. In paragraph 1, A semiconductor device in which the upper electrode structure further comprises a stacked structure of a silicon germanium layer and a tungsten layer on the crystalline titanium nitride.
9. In paragraph 1, A semiconductor device comprising a first lower electrode including a cylinder structure and a second lower electrode provided inside the first lower electrode, having a grain size smaller than the grain size of the first lower electrode and including a pillar structure.
10. In Paragraph 9, A semiconductor device in which the hardness of the second lower electrode is greater than the hardness of the first lower electrode.
11. In Paragraph 9, A semiconductor device in which the first lower electrode comprises a metal nitride and the second lower electrode comprises a metal silicon nitride.
12. In Paragraph 9, The first lower electrode is a semiconductor device comprising any one of titanium nitride, tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN) or tungsten nitride (WN).
13. In Paragraph 9, The second lower electrode is a semiconductor device comprising titanium silicon nitride.
14. In paragraph 1, A semiconductor device comprising a first lower electrode including a cylinder structure, a second lower electrode formed along the inner surface of the first lower electrode and including a cylinder structure having a grain size smaller than the grain size of the first lower electrode, and a third lower electrode provided inside the second lower electrode and including a pillar structure.
15. In Paragraph 14, A semiconductor device in which the first lower electrode comprises a metal nitride, the second lower electrode comprises a metal silicon nitride, and the third lower electrode comprises polysilicon.
16. In paragraph 1, A semiconductor device comprising a conductive material layer having a grain size smaller than the grain size of titanium nitride, wherein the lower electrode structure includes a pillar structure.
17. In paragraph 1, The above lower electrode structure is a semiconductor device composed of titanium silicon nitride including a pillar structure.
18. In paragraph 1, A semiconductor device further comprising a supporter that supports the outer wall of the lower electrode structure.
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Description

Semiconductor Device and Method for Fabricating the Same The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a capacitor of a semiconductor device and a method for manufacturing the same. With the integration of semiconductor devices, issues regarding the difficulty of ensuring continuity due to bending of the lower electrode and the reduction in the thickness of the upper electrode are emerging. Consequently, this can lead to degradation of capacitor characteristics. FIGS. 1 to 6 are cross-sectional views illustrating capacitors according to the embodiments of the present invention. FIGS. 7a to 7h are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the present embodiment. FIG. 8 is a timing diagram for forming titanium silicon nitride of the lower electrode according to the present embodiment. FIG. 9 is a timing diagram for forming an upper electrode according to the present embodiment. The embodiments described herein will be explained with reference to cross-sectional views, plan views, and block drawings, which are ideal schematic diagrams of the invention. Accordingly, the shapes of the exemplary drawings may be modified due to manufacturing techniques and/or tolerances, etc. Therefore, the embodiments of the invention are not limited to the specific shapes depicted but include variations in shape resulting from the manufacturing process. Accordingly, the regions illustrated in the drawings have schematic properties, and the shapes of the regions illustrated in the drawings are intended to illustrate specific forms of the regions of the device and are not intended to limit the scope of the invention. FIGS. 1 to 6 are drawings illustrating capacitors according to the embodiments of the present invention. FIG. 8 is a timing diagram for forming titanium silicon nitride of the lower electrode according to the present invention. FIG. 9 is a timing diagram for forming the upper electrode according to the present invention. As illustrated in FIG. 1, the semiconductor device includes a substrate (101), an interlayer insulating layer (102) formed on the substrate (101), and storage node contact structures (103, 104) that penetrate the interlayer insulating layer (102) and connect to the substrate (101). The semiconductor device further includes a capacitor structure formed on the interlayer insulating layer (102). The capacitor structure includes a lower electrode structure (110) connected to the storage node contact structures (103, 104), a dielectric layer (120) covering the entire structure including the lower electrode structure (110), and an upper electrode structure (130) formed on the dielectric layer (120). The substrate (101) may be a material suitable for semiconductor processing. The substrate (101) may include a semiconductor substrate. The substrate (101) may be made of a material containing silicon. The substrate (101) may include silicon, single-crystal silicon, polysilicon, amorphous silicon, silicon germanium, single-crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multilayers thereof. The substrate (101) may include other semiconductor materials such as germanium. The substrate (101) may include a group III/V semiconductor substrate, such as a compound semiconductor substrate like GaAs. The substrate (101) may include a Silicon On Insulator (SOI) substrate. Although not shown, a buried gate structure may be placed within the substrate (101), and a bit line structure may be placed between the storage node contact structures (103, 104) on the substrate (101). The interlayer insulating layer (102) may include a single layer or a multilayer insulating material. The interlayer insulating layer (102) may include a multilayer insulating material with the same etching selectivity. The interlayer insulating layer (102) may include a multilayer insulating material with different etching selectivity. The interlayer insulating layer (102) may include a nitride, an oxide, an oxynitride, or a combination thereof. The storage node contact structure (103, 104) can be connected to the substrate (101) by penetrating the interlayer insulation layer (102). One end of the storage node contact plug (103, 104) can be in direct contact with a bonding area (not shown) of the substrate (101). The other end of the storage node contact plug (103, 104) can be in direct contact with the lower electrode structure (110). The storage node contact plug (103, 104) can electrically connect the substrate (101) and the lower electrode structure (110). The storage node contact structure (103, 104) may be a stack of a lower plug (103) and an upper plug (104). The lower plug (103) may include a silicon plug. The upper plug (104) may include a metal plug. The lower electrode structure (110) may include a first lower electrode (111) having a cylinder structu