KR-102962459-B1 - Uplink power control to improve physical uplink channel reliability

KR102962459B1KR 102962459 B1KR102962459 B1KR 102962459B1KR-102962459-B1

Abstract

The present application relates to devices and components including devices, systems, and methods for uplink power control for channels having repetitions.

Inventors

장, 유슈
젱, 웨이
양, 웨이동
야오, 춘하이
예, 춘쑤안
장, 다웨이
순, 하이통
허, 홍
니우, 화닝
파쿠리안, 세예드 알리 아크바르
예, 시겐

Assignees

애플 인크.

Dates

Publication Date: 20260511
Application Date: 20210108

Claims (20)

A computer-readable storage medium having instructions, wherein, when executed, the instructions cause a processing circuit to, Processing power control (PC) configuration information for communication within a frequency range of 410 megahertz (MHz) to 7125 MHz received from a base station outside the physical uplink control channel (PUCCH) spatial relationship configuration; Selecting first power control parameters to be used in the first repetition of physical uplink control channel (PUCCH) transmission from the above power control configuration information; Selecting second power control parameters to be used for the second repetition of the PUCCH transmission from the above power control configuration information; Generating a first repetition of the PUCCH transmission with the first power control parameters; A computer-readable storage medium that generates a second repetition of the PUCCH transmission using the second power control parameters.
A computer-readable storage medium according to claim 1, wherein the power control configuration information is for configuring a set of P0 and a plurality of path loss reference signals (RS); the first power control parameters include a first P0 from the set of P0 and a first path loss reference RS from the plurality of path loss reference RSs; and the second power control parameters include a second P0 from the set of P0 and a second path loss reference RS from the plurality of path loss reference RSs.
A computer-readable storage medium according to claim 1, wherein the power control configuration information is for configuring first and second sets of P0 and first and second plurality of path loss reference signals (RS); the first power control parameters include a first P0 from the first set of P0 and a first path loss reference RS from the first plurality of path loss reference RSs; and the second power control parameters include a second P0 from the second set of P0 and a second path loss reference RS from the second plurality of path loss reference RSs.
In paragraph 1, when the above instructions are executed, additionally cause the processing circuit to, Multiple closed-loop power control processes detect that they are enabled for PUCCH; Applying a first closed-loop power control process to the first iteration of the above PUCCH transmission; A computer-readable storage medium that applies a second closed-loop power control process to a second repetition of the above PUCCH transmission.
A computer-readable storage medium according to claim 1, wherein the processing circuit is for receiving power control configuration information from a PUCCH power control information element (IE) by wireless resource control signaling.
In claim 1, the power control configuration information is for configuring at least two sets of power control (PC) parameters, and the instructions, when executed, additionally cause the processing circuit to, A computer-readable storage medium that maps at least two sets of PC parameters to a plurality of iterations of the PUCCH transmission based on a cyclic mapping pattern or a sequential mapping pattern, wherein the plurality of iterations includes the first iteration and the second iteration, the cyclic mapping pattern is for cyclically mapping sets of PC parameters mapped to consecutive iterations, and the sequential mapping pattern is for mapping individual sets of PC parameters to consecutive iterations.
A computer-readable storage medium according to claim 1, wherein, when the instructions are executed, the processing circuit additionally receives power control configuration information for configuring a plurality of power control parameters through radio resource control (RRC) signaling.
A computer-readable storage medium, wherein, in paragraph 7, the instructions, when executed, additionally cause the processing circuit to receive a media access control (MAC) control element (CE) for activating the first power control parameters and the second power control parameters from the plurality of power control parameters.
A computer-readable storage medium according to claim 8, wherein the processing circuit is for receiving the MAC CE in a first serving cell, and the MAC CE is for configuring one or more power control parameters for a PUCCH resource or a group of PUCCH resources for a second serving cell or a plurality of serving cells in a list of serving cells configured by RRC signaling.
In paragraph 7, when the above instructions are executed, additionally cause the processing circuit to: By receiving the power control configuration information for configuring a plurality of power control parameters through RRC signaling; A computer-readable storage medium that receives a media access control (MAC) control element (CE) for activating the first power control parameters and the second power control parameters from the plurality of power control parameters.
A computer-readable storage medium according to claim 7, wherein the PUCCH resource is a first PUCCH resource, and the instructions, when executed, additionally cause the processing circuit to receive the power control configuration information as a configuration of both the first PUCCH resource and the second PUCCH resource; and to receive from the base station an instruction to transmit the same uplink control information in both the first and second PUCCH resources.
A computer-readable storage medium according to claim 1, wherein, when the instructions are executed, the processing circuit unit additionally receives the power control configuration information as a configuration of a plurality of power control parameter sets; and additionally receives a representation of at least one of the plurality of power control parameter sets through downlink control information (DCI) signaling.
As a method performed by a processing circuit, A step of receiving power control (PC) configuration information for frequency range 1 (FR1) communication from a base station outside the physical uplink control channel (PUCCH) spatial relationship configuration; A step of selecting first power control parameters to be used in a first repetition of physical uplink control channel (PUCCH) transmission from the above power control configuration information; A step of selecting second power control parameters to be used for a second repetition of the PUCCH transmission from the power control configuration information; A step of generating a first repetition of the PUCCH transmission with the first power control parameters applied to the first beam; and A step of generating a second repetition of the PUCCH transmission using the second power control parameters applied to the second beam. A method including
In claim 13, the power control configuration information is for configuring a set of P0 and a plurality of path loss reference signals (RS); the first power control parameters include a first P0 from the set of P0 and a first path loss reference RS from the plurality of path loss reference RSs; and the second power control parameters include a second P0 from the set of P0 and a second path loss reference RS from the plurality of path loss reference RSs.
In Paragraph 13, A step of detecting that multiple closed-loop power control processes are enabled for PUCCH; A step of applying a first closed-loop power control process to the first repetition of the above PUCCH transmission; Step of applying a second closed-loop power control process to the second iteration of the above PUCCH transmission A method that additionally includes
In paragraph 13, the power control configuration information is for configuring at least two sets of power control (PC) parameters, and the method is, A step of mapping the at least two sets of PC parameters to a plurality of repetitions of the PUCCH transmission based on a cyclic mapping pattern or a sequential mapping pattern. A method further comprising, wherein the cyclic mapping pattern is for cyclically mapping sets of PC parameters mapped to consecutive iterations, and the sequential mapping pattern is for mapping individual sets of PC parameters to consecutive iterations.
In Paragraph 13, A step of receiving power control configuration information for configuring a plurality of power control parameters through wireless resource control (RRC) signaling; and A step of receiving a media access control (MAC) control element (CE) for activating the first power control parameters and the second power control parameters from the plurality of power control parameters. A method that additionally includes
As a method performed by a processing circuit, A step of generating power control configuration information for communication within frequency range 1 (FR1) for transmission to user equipment (UE) outside the physical uplink control channel (PUCCH) spatial relationship configuration; A step of receiving a first repetition of PUCCH transmission with first power control parameters selected from the power control configuration information applied to the first beam; and A step of receiving a second repetition of the PUCCH transmission with second power control parameters selected from the power control configuration information applied to the second beam. A method including
In Paragraph 18, A step of generating power control configuration information for transmission to configure a plurality of power control parameters through wireless resource control (RRC) signaling. A method of additionally including.
In Paragraph 19, A step of generating a Media Access Control (MAC) control element (CE) for transmission to the UE to activate the first power control parameters and the second power control parameters from the plurality of power control parameters. A method of additionally including.

Description

Uplink power control to improve physical uplink channel reliability The Third Generation Partnership Project (3GPP) provides uplink power control (PC) to provide effective uplink communication while limiting interference and power consumption at user equipment (UE). Power control parameters may be provided to the UE to control uplink power. In 3GPP Releases 15 and 16, power control parameters are derived as follows. If a spatial relationship is configured, the power control parameters are configured within the spatial relationship configuration. The spatial relationship is applicable only to Frequency Range 2 (FR2), 24,250 megahertz (MHz) to 52,600 MHz. If a spatial relationship is not configured, default power control parameters may be selected from the first power control parameters within the list of power control parameters configured by radio resource control (RRC) signaling. FIG. 1 illustrates a network environment according to some embodiments. FIG. 2 includes a set of power control parameters for iterative mapping according to some embodiments. FIG. 3 illustrates two scenarios for signaling sets of power control parameters according to some embodiments. FIG. 4 illustrates slot hopping according to some embodiments. FIG. 5 illustrates the operation flow/algorithm structure according to some embodiments. FIG. 6 illustrates different operation flow/algorithm structures according to some embodiments. FIG. 7 illustrates different operation flow/algorithm structures according to some embodiments. FIG. 8 illustrates beamforming components of a device according to some embodiments. FIG. 9 illustrates user equipment according to some embodiments. FIG. 10 illustrates a gNB according to some embodiments. The following detailed description refers to the accompanying drawings. The same reference numbers may be used in different drawings to identify identical or similar elements. In the following description, specific details such as specific structures, architectures, interfaces, techniques, etc., are described for the purpose of explanation rather than limitation, to provide a thorough understanding of various aspects of various embodiments. However, it will be apparent to those skilled in the art who have an interest in the present disclosure that various aspects of various embodiments may be practiced in other examples other than these specific details. In certain cases, descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of various embodiments with unnecessary details. For the purposes of this specification, the phrase “A or B” means (A), (B), or (A and B). The following is an explanation of terms that may be used in this disclosure: The term “circuit part” as used herein refers to, is part of, or includes hardware components such as electronic circuits, logic circuits, processors (shared, dedicated, or group), or memory (shared, dedicated, or group), application-specific integrated circuits (ASICs), field-programmable devices (FPDs) (e.g., field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), complex PLDs (CPLDs), high-capacity PLDs (HCPLDs), structured ASICs, or programmable SoCs (system-on-a-chip)), digital signal processors (DSPs), etc., configured to provide the described functions. In some embodiments, the circuit part may execute one or more software or firmware programs to provide at least some of the described functions. The term “circuit part” may also refer to a combination of one or more hardware elements (or a combination of circuits used in an electrical or electronic system) and the program code used to perform the function of the program code. In these embodiments, the combination of hardware elements and program code may be referred to as a specific type of circuit part. As used herein, the term “processor circuit” refers to, is part of, or includes a circuit capable of performing a sequence of arithmetic or logical operations sequentially and automatically, or recording, storing, or transmitting digital data. The term “processor circuit” may refer to an application processor, baseband processor, central processing unit (CPU), graphics processing unit, single-core processor, dual-core processor, triple-core processor, quad-core processor, or any other device capable of executing or otherwise operating computer-executable instructions, such as program code, software modules, or functional processes. As used herein, the term “interface circuit” refers to, is part of, or includes a circuit that enables the exchange of information between two or more components or devices. The term “interface circuit” may refer to one or more hardware interfaces, e.g., buses, I/O interfaces, peripheral component interfaces, network interface cards, etc. As used herein, the term "user equipment" or "UE" refers to a device having wireless communication capabilities and may describe a remote user of network resources in a communication netw