KR-102962519-B1 - Integrator for low-power, high-resolution analog-to-digital converter and its operating method

KR102962519B1KR 102962519 B1KR102962519 B1KR 102962519B1KR-102962519-B1

Abstract

The present invention relates to an integrator for a low-power, high-resolution analog-to-digital converter and a method of operation thereof. The integrator for a low-power, high-resolution analog-to-digital converter according to the present invention comprises: an operational amplifier that converts an analog input signal into a current signal; an integrating capacitor connected to the operational amplifier that integrates a current corresponding to the analog input signal and stores an integrated voltage; and a DCT switching module having at least one switching section controlled by a clock signal that controls the integration operation of the integrating capacitor. The present invention can provide a DCT circuit capable of adjusting the Gm of the integrator in an analog-to-digital converter to a desired value.

Inventors

노정진
윤상인
신화성

Assignees

한양대학교 에리카산학협력단

Dates

Publication Date: 20260507
Application Date: 20231226

Claims (14)

As an integrator for a low-power, high-resolution analog-to-digital converter, An operational amplifier that converts an analog input signal into a current signal; An integrating capacitor connected to the above operational amplifier and storing an integrated voltage by integrating a current corresponding to the analog input signal; and A DCT switching module having at least one switching unit controlled by a clock signal that controls the integration operation of the integration capacitor; comprising, The above DCT switching module is an integrator for an analog-to-digital converter that performs the role of a duty cycle transconductance, which controls the amount of charge stored in the integrating capacitor by adjusting the transconductance of the operational amplifier in proportion to the duty cycle of the clock signal.
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In paragraph 1, The role of the duty cycle transconductance of the above DCT switching module is, An integrator for an analog-to-digital converter that increases linearity and reduces noise in the integrator by using source degeneration and Gm boosting techniques on the transconductance of the operational amplifier, while simultaneously reducing the physical size of the integrating capacitor (C_int).
In paragraph 1, The above DCT switching module includes a first switching unit and a second switching unit, and An integrator for an analog-to-digital converter, wherein the first switching unit and the second switching unit sequentially control the current flow from the operational amplifier to control the charging and discharging timing of the integrating capacitor.
In paragraph 4, An integrator for an analog-to-digital converter, wherein the first switching unit and the second switching unit operate in synchronization with the clock signal, and the first clock signal controlling the first switching unit and the second clock signal controlling the second switching unit have an inverted relationship.
In paragraph 5, The above clock signal is generated by a clock generator, and The above clock generator is, An inverter chain that determines the signal delay as a clock input signal input from the outside passes through; and A NAND gate that uses the output of the last inverter of the inverter chain as a first input and a signal branched between the first and second inverters of the inverter chain as a second input to generate an output signal based on the time difference between the first input and the second input; and Includes an additional inverter that inverts the output signal of the above NAND gate; and An integrator for an analog-to-digital converter, wherein the clock generator generates the clock signal based on the output signal of the NAND gate and the output signal of the additional inverter.
In paragraph 6, An integrator for an analog-to-digital converter, wherein the transconductance of the operational amplifier is controlled by the clock generator.
In Paragraph 7, An integrator for an analog-to-digital converter, wherein the transconductance of the operational amplifier is controlled by only two switching units, including the first switching unit and the second switching unit synchronized with the clock signal.
In paragraph 8, The above operational amplifier outputs the converted current signal to the first node, and One end of the first switching unit is connected to the first node and the other end is connected to the second power source, and One end of the second switching unit is connected to the first node and the other end is connected to the second node, and The above integrating capacitor is an integrator for an analog-to-digital converter, connected to the operational amplifier at the second node.
In Paragraph 9, The second node above is an integrator for an analog-to-digital converter corresponding to the output voltage of the integrator.
In paragraph 1, The above switching unit is an integrator for an analog-to-digital converter, which is a p-channel MOSFET transistor.
As a method of operation of an integrator for a low-power, high-resolution analog-to-digital converter, The integrator for the above low-power, high-resolution analog-to-digital converter is, An operational amplifier that amplifies an analog input signal and outputs it as a current signal; and It includes an integrating capacitor connected to the above operational amplifier and storing an integrated voltage by integrating a current corresponding to the analog input signal; A DCT switching module having at least one switching unit controlled by a clock signal that controls the integration operation of the integration capacitor; further comprising The method includes the step of sequentially controlling the current flow from the operational amplifier to the integrating capacitor to control the charging and discharging timing of the integrating capacitor; The control of the above charging and discharging timing is, A step of integrating the output current signal according to the duty ratio of the first clock signal and storing the integrated voltage; and A method comprising the step of resetting the integrated voltage according to the duty ratio of the second clock signal.
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In Paragraph 12, A method in which the first clock signal and the second clock signal have an inverted relationship.

Description

Integrator for low-power, high-resolution analog-to-digital converter and its operating method The present invention relates to an integrator for a low-power, high-resolution analog-digital converter and a method of operation thereof, and more specifically, to an integrator for a low-power, high-resolution analog-digital converter comprising a DCT (Duty cycle transconductance) block capable of adjusting the Gm of the integrator to a desired value and a method of operation thereof. Recently, active research is being conducted on low-power, high-resolution analog-to-digital converters required for medical devices and touch sensors. In analog-to-digital converters (ADCs), the delta-sigma modulator plays a crucial role in achieving the high-resolution characteristics of the converter. In a delta-sigma modulator, the integrator is one of the core components of an analog-to-digital converter. The integrator performs the integration of the analog input signal to generate a modulated signal. The integrator structures primarily used in Continuous-Time Delta-Sigma Modulators (CTDSMs) are Active-RC and Gm-C structures. Figure 1 shows an active-RC structure integrator. Rint and Cint represent the resistor and capacitor of the integrator, respectively. As illustrated in the figure, the active-RC structure integrator can accurately perform the integration of an input signal through an RC filter and a transconductance amplifier, thereby possessing high linearity. In the active-RC integrator, a closed loop is primarily used to ensure the accurate operation of the integrator. The integrator generates an output signal by integrating the input signal, and the operation of the integrator can be controlled and corrected through closed-loop feedback. Figure 2 shows an integrator with a Gm-C structure. Cint represents the capacitor of the integrator. The Gm-C structure integrator consists of a voltage control source (transconductance amplifier, Gm) and a capacitor (Cint). In this structure, the Gm block performs integration by controlling the current flowing through Cint. When an input signal is applied to the Gm block, the Gm block controls the voltage of the input signal to regulate the current flowing through Cint. The regulated current is accumulated in Cint, representing the accumulation of the input signal. This accumulated voltage is then passed to the next stage to undergo the modulation and oversampling processes of an analog-to-digital converter. Gm-C integrators have relatively lower current consumption compared to active RC integrators because they lack a feedback loop. However, linearity is constrained by their open-loop characteristics, and techniques to address this must be applied to the implementation of the Gm-C structure. Generally, low-power delta-sigma modulator designs use integrators with a Gm-C structure that consume relatively little power. Meanwhile, in the design of low-power delta-sigma modulators, the Gm-C structure has the disadvantage of poor linearity, so a method to increase the stability of the modulator by reducing the integrator output swing is considered. At this time, the noise transfer function gain (NTF gain) value to maintain the stability of the third-order delta-sigma modulator and the coefficients determined according to the output swing of each integrator can be expressed as Equation 1 below, and the values of Gm and Cint are determined according to this equation. In this equation, Gm represents the voltage control source of the integrator, Cint represents the capacitor of the integrator, and Fs represents the sampling frequency. In other words, in the design of high-resolution, low-power delta-sigma modulators, a Gm-C integrator structure is used instead of an active RC integrator because it consumes relatively less power and is free from thermal noise caused by input resistance; however, since the Gm-C structure has the disadvantage of poor linearity, the output swing of the integrator is set to be as small as possible to compensate for this. The output swing can be determined by adjusting an appropriate value based on the noise transfer function (NTF) gain value, which represents the stability of the delta-sigma modulator, through simulations such as MATLAB. The equation satisfied in this case can be expressed as Equation 1 above, and the smaller the value of the coefficient in the above equation, the smaller the output swing of each integrator becomes. At this time, to reduce the coefficient value, there are methods to lower the Gm value of the integrator or increase the value of Cint. However, there are limitations to actually implementing a small Gm value. This is because the Gm-C structure, as shown in Fig. 3, uses source degeneration and Gm boosting techniques to ensure linearity. This method increases the Gm of transistors Q1 and Q2 without increasing the current of Q1 and Q2, and fixes the Gm of the integrator at 1/ Rs to improve linearity and reduce noise in the integrator.