KR-102962521-B1 - LOW-TEMPERATURE DEUTERIUM ANNEALING METHOD FOR ENHANCING SURFACE ROUGHNESS AND UNIFORMITY OF THIN FILM, AND SEMICONDUCTOR DEVICE MANUFACTURED BY THE SAME

Abstract

A low-temperature deuterium annealing method according to the present invention comprises the steps of providing a silicon substrate, forming a thin film on the silicon substrate using at least one of an oxidation process, a deposition process, and an etching process, and performing a low-temperature deuterium heat treatment on the thin film to improve the roughness and uniformity of the thin film, wherein the low-temperature deuterium heat treatment is performed for 0.1 to 10 hours at a deuterium concentration of 50% or less, a temperature of 300°C or less, and a pressure of 5 to 40 bar. The low-temperature deuterium annealing method according to the present invention is applied to the manufacturing process of miniaturized FinFET and GAA FET (Gate-All-Around FET) devices to improve the roughness and uniformity of the thin film, thereby enabling improvement in the performance and yield of the device.

Inventors

• 박준영
• 연주원
• 길태현
• 박효준
• 최유진
• 강상민
• 지홍석

Assignees

• 충북대학교 산학협력단

Dates

Publication Date

20260511

Application Date

20240422

Claims (10)

1. A step of patterning a silicon substrate to form a pin region; A step of performing a low-temperature deuterium heat treatment process on the silicon substrate and pin region; A step of forming a Shallow Trench Isolation (STI) for isolation between devices; A step of performing the above low-temperature deuterium heat treatment on the above STI; A step of forming a first thin film in the above pin region; A step of performing the low-temperature deuterium heat treatment on the first thin film; A step of forming a second thin film on the first thin film on which the above low-temperature deuterium heat treatment has been performed; A step of performing the low-temperature deuterium heat treatment again on the second thin film; and The method includes the step of depositing a gate on the above STI and the above second thin film; The above low-temperature deuterium heat treatment is performed at a deuterium concentration of 50% or less and a temperature of 300℃ or less, and The first thin film above is a SiO2 thin film formed by an oxidation process, and A low-temperature deuterium annealing method in which the second thin film is an HfO2 thin film formed by a deposition process.
2. In paragraph 1, The above low-temperature deuterium heat treatment is a low-temperature deuterium annealing method performed at a pressure of 5 to 40 bar.
3. In paragraph 1, A low-temperature deuterium annealing method in which the above low-temperature deuterium heat treatment is performed for 0.1 to 10 hours.
4. delete
5. A step of alternately depositing Si and SiGe on a silicon substrate; A step of performing low-temperature deuterium heat treatment on the stack structure of the above Si and SiGe; A step of depositing Dummy Poly-Si and an external spacer on the stack structure above, and then etching the source region and the drain region; A step of etching a portion of the SiGe of the stack structure and forming an internal spacer, and then forming a source and a drain in the source region and the drain region, respectively, through epitaxial growth; A step of removing the above Dummy Poly-Si and the above SiGe, and forming a first thin film in the removal area; A step of performing low-temperature deuterium heat treatment on the first thin film; A step of forming a second thin film on the first thin film on which the above low-temperature deuterium heat treatment has been performed; A step of performing the low-temperature deuterium heat treatment again on the second thin film; and The method includes the step of depositing a gate on the second thin film; The above low-temperature deuterium heat treatment is performed at a deuterium concentration of 50% or less and a temperature of 300℃ or less, and The first thin film above is a SiO2 thin film formed by an oxidation process, and A low-temperature deuterium annealing method in which the second thin film is an HfO2 thin film formed by a deposition process.
6. In paragraph 5, The above low-temperature deuterium heat treatment is a low-temperature deuterium annealing method performed at a pressure of 5 to 40 bar.
7. In paragraph 5, A low-temperature deuterium annealing method in which the above low-temperature deuterium heat treatment is performed for 0.1 to 10 hours.
8. delete
9. delete
10. A semiconductor device manufactured by the low-temperature deuterium annealing method described in any one of claims 1 to 3 and claims 5 to 7.

Description

Low-temperature deuterium annealing method for enhancing surface roughness and uniformity of thin film and semiconductor device manufactured thereby The present invention relates to a low-temperature deuterium annealing method for improving the surface roughness and uniformity of a thin film formed on a silicon substrate and to a semiconductor device manufactured thereby. Currently, the semiconductor industry is continuously conducting research on miniaturization for high performance, high integration, and high productivity. However, as the physical size of the gate length and channel width of semiconductor devices shrinks to extreme levels of 10 nm or less, it has become very difficult to control the surface roughness of the silicon channel. The rough surface of silicon not only degrades the output performance of the device due to scattering but also affects subsequent processes and causes problems that reduce chip yield by inducing misalignment and contrast degradation. Accordingly, many studies have been attempted to improve the roughness of thin films containing silicon in order to maximize chip yield. Korean Patent Publication No. 10-2001-0028418 (Title of Invention: Method for Manufacturing a Semiconductor Wafer with Annealing and Method for Manufacturing a Semiconductor Device) discloses an annealing process that cures crystal defects present on the surface of a semiconductor wafer or semiconductor substrate by annealing. However, since this conventional process is carried out in an environment of high temperature of 400°C or higher and 100% hydrogen gas concentration, it causes another problem involving disadvantages such as degradation of device characteristics due to high temperature and increased process costs due to the use of high-concentration gas. Figure 1 is a flowchart of a low-temperature deuterium annealing method according to the present invention. Figure 2 is a flowchart showing the case where the low-temperature deuterium annealing method according to the present invention is applied to the manufacture of a Fin FET. FIG. 3 is a diagram illustrating each process when the low-temperature deuterium annealing method according to the present invention is applied to the manufacture of a Fin FET. Figure 4 is a flowchart showing the case where the low-temperature deuterium annealing method according to the present invention is applied to the manufacture of a nanosheet device. FIG. 5 is a diagram illustrating each process when the low-temperature deuterium annealing method according to the present invention is applied to the manufacture of a nanosheet device. Figures 6 and 7 show the results of an Atomic Force Microscope (AFM) experiment when the low-temperature deuterium annealing method according to the present invention is applied to a thin film formed through an oxidation process. Figures 8 and 9 show the results of an Atomic Force Microscope (AFM) experiment when the low-temperature deuterium annealing method according to the present invention is applied to a thin film formed through a deposition process. Figure 10 is a graph showing the effect of improving thin film uniformity by the low-temperature deuterium annealing method according to the present invention. FIGS. 11a to 11c illustrate the results of an Atomic Force Microscope (AFM) experiment when the low-temperature deuterium annealing method according to the present invention is applied to a thin film that has undergone a CMP process. Hereinafter, embodiments disclosed in this specification will be described in detail with reference to the attached drawings. Identical or similar components regardless of drawing symbols will be assigned the same reference number, and redundant descriptions thereof will be omitted. The suffix "bu" for components used in the following description is assigned or used interchangeably solely for the ease of drafting the specification and does not have a distinct meaning or role in itself. Furthermore, in describing the embodiments disclosed in this specification, if it is determined that a detailed description of related prior art could obscure the essence of the embodiments disclosed in this specification, such detailed description will be omitted. Additionally, the attached drawings are intended only to facilitate understanding of the embodiments disclosed in this specification; the technical concept disclosed in this specification is not limited by the attached drawings, and it should be understood that they include all modifications, equivalents, and substitutions that fall within the spirit and technical scope of the present invention. Hereinafter, embodiments according to the present invention will be described in detail with reference to the attached drawings. The low-temperature deuterium annealing method according to the present invention is intended to improve the surface roughness and uniformity of a thin film, and the heat treatment process can be carried out in an environment having a deuteri