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KR-102962536-B1 - SEMICONDUCTOR MEMORY DEVICE, CONTROL METHOD AND CONTROL DEVICE

KR102962536B1KR 102962536 B1KR102962536 B1KR 102962536B1KR-102962536-B1

Abstract

[Problem] To provide a semiconductor memory device, etc., capable of suppressing malfunctions caused by manufacturing variations of transistors constituting a sensing amplifier without changing the configuration of the sensing amplifier itself. [Solution] A semiconductor memory device comprises a plurality of word lines and bit lines, a memory cell array (111) composed of a plurality of memory cells connected to one of the word lines and bit lines, and a detection amplifier (13) connected to the bit line. The semiconductor memory device comprises a control unit that, while changing a parameter regarding the condition of the detection operation of the detection amplifier (13), counts the number of memory cells with a reading error in which a value different from the expected value is read during a data reading operation from the memory cells, and adjusts the value of the parameter so that the number of memory cells with a corresponding operation failure becomes the minimum, thereby minimizing the number of memory cells with the reading error memory cells.

Inventors

  • 사토 타카히코

Assignees

  • 윈본드 일렉트로닉스 코포레이션

Dates

Publication Date
20260508
Application Date
20230509
Priority Date
20230328

Claims (14)

  1. Multiple word lines and bit lines, and, A memory cell array comprising a plurality of memory cells connected to one of the plurality of word lines and the bit line, and A sensing amplifier connected to the above bit line, and Including the coordination department, The above adjustment unit is, In a read operation, count the number of read error memory cells for "1" data and the number of read error memory cells for "0" data, and determine the side with the higher number of read error memory cells; If either the number of memory cells with read error for the "1" data or the number of memory cells with read error for the "0" data is greater than or equal to a predetermined value, adjust the parameter; When the address of the above memory cell reaches the end address, the parameter is configured to be adjusted based on the more side read error memory cell, and The above adjustment unit adjusts the parameter to have a parameter value that minimizes the total number of read error memory cells; The above-mentioned read error memory cell has a reading value different from the expected value during the data reading operation of the memory cell; A semiconductor memory device characterized in that the above parameter is related to the conditions of the sensing operation of the above sensing amplifier.
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  4. In paragraph 1, The above memory cell array includes spare cells, and A semiconductor memory device characterized by performing a redundancy rescue using a corresponding spare cell for memory cells having a read error in the parameter after the value of the parameter is adjusted by the adjustment unit so that the total number of read error memory cells is minimized.
  5. In paragraph 4, A semiconductor memory device characterized by performing a redundancy repair using a spare cell for a memory cell in which a read error exists in the parameter value within a predetermined range from the value of the parameter.
  6. In paragraph 1, A semiconductor memory device characterized in that the above-described sensing amplifier is a cross-coupled latch type sensing amplifier comprising two nMOS transistors and two pMOS transistors connected between a pair of bit lines.
  7. In paragraph 6, A semiconductor memory device characterized in that the above parameter is at least one of the back bias voltage of an nMOS transistor constituting the sensing amplifier, the power supply voltage of the sensing amplifier, and the balanced voltage between a pair of bit lines.
  8. In paragraph 1, A semiconductor memory device characterized by including a first comparator that receives expected data information consisting of multiple bits that do not contain errors and read data information consisting of multiple bits read from a memory cell array, and generates error information from the read data information to determine whether the read error exists in any of the memory cells during a read operation of "1" or "0" of the memory cells.
  9. In paragraph 1, A semiconductor memory device characterized by being configured to emit an alarm when either the number of memory cells with read errors for the "1" data or the number of memory cells with read errors for the "0" data is greater than the predetermined value.
  10. In paragraph 1, A semiconductor memory device characterized by the above adjustment unit including an ECC unit that performs error detection and correction, and generating error information that specifies whether the read error exists in any of the memory cells during a read operation of either "1" or "0" by performing error detection by the above ECC unit.
  11. In paragraph 1, The above adjustment unit, while fixing the above parameters and selecting memory cells in a predetermined order, counts the number of memory cells in which a read error exists in each parameter, A semiconductor memory device characterized by being configured not to continuously select memory cells connected to the same word line.
  12. In paragraph 1, A semiconductor memory device characterized in that the above-described semiconductor memory device is a volatile memory.
  13. Multiple word lines and one bit line, and, A memory cell array comprising a plurality of memory cells connected to one of the plurality of word lines and one bit line, and A control method for a semiconductor memory device including a sensing amplifier connected to bit lines, A step of counting the number of read error memory cells for "1" data and the number of read error memory cells for "0" data in a read operation, and determining the side with more read error memory cells; A step of adjusting a parameter when either the number of memory cells with read error for the "1" data or the number of memory cells with read error for the "0" data is greater than or equal to a predetermined value; A step of adjusting the parameter based on the more side read error memory cell when the address of the memory cell reaches the end address; and It includes a step of adjusting the parameter to have a parameter value that minimizes the total number of read error memory cells, and The above-mentioned read error memory cell has a reading value different from the expected value during the data reading operation of the memory cell; A control method for a semiconductor memory device characterized in that the above parameters are related to the conditions of the sensing operation of the above sensing amplifier.
  14. Multiple word lines and one bit line, and, A memory cell array comprising a plurality of memory cells connected to one of the plurality of word lines and one bit line, and Sensing amplifier connected to bit lines A control device installed in a semiconductor memory device including, The above control device counts the number of memory cells with read error for "1" data and the number of memory cells with read error for "0" data in a read operation, and determines which side has more memory cells with read error; The control device adjusts a parameter when either the number of memory cells with read errors for the "1" data or the number of memory cells with read errors for the "0" data is greater than or equal to a predetermined value; The control device adjusts the parameter based on the more side read error memory cell when the address of the memory cell reaches the end address; The above control device adjusts the parameter to have a parameter value that minimizes the total number of read error memory cells; The above-mentioned read error memory cell has a reading value different from the expected value during the data reading operation of the memory cell; A control device characterized in that the above parameter is related to the conditions of the detection operation of the above detection amplifier.

Description

Semiconductor Memory Device, Control Method and Control Device The present invention relates to a semiconductor memory device, a control method, and a control device. A semiconductor memory device is provided with a memory cell array composed of a plurality of memory cells, and a sensing amplifier is installed corresponding to a plurality of bit lines connected to the memory cell array. When reading data, the sensing amplifier detects and amplifies data read from the memory cell to the bit line, and when writing data, transmits the written data to the bit line. Although cross-coupled latch types are known as sensing amplifiers, if there is a mismatch (e.g., a mismatch in threshold voltage) caused by manufacturing variations in the components constituting the sensing amplifier, invalid sensing may occur, potentially leading to malfunction. To suppress such malfunctions, a sensing amplifier with a configuration that is less susceptible to the influence of deviations in transistor characteristics, such as Patent Document 1, is known. FIG. 1 is a schematic block diagram showing a semiconductor memory device according to embodiment 1. FIG. 2 is a schematic diagram illustrating the configuration of a memory cell array. Figure 3 is a schematic diagram illustrating the relationship between a sensing amplifier and a memory cell. FIG. 4 is a diagram showing the voltage change of bit lines (bl, blx) in detection. FIG. 5 is a diagram showing the voltage change of bit lines (bl, blx) in detection. Figure 6 is a diagram showing the relationship between the number of malfunctioning cells Y and the parameter X. FIG. 7 is a flowchart for explaining control by the adjustment unit. FIG. 8 is a schematic block diagram showing a semiconductor memory device according to embodiment 2. FIG. 9 is a schematic block diagram for explaining the configuration of a semiconductor memory device. Hereinafter, a control device, a control method, and a semiconductor memory device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, this embodiment is illustrative and the present invention is not limited thereto. (Embodiment 1) FIG. 1 is a block diagram of a semiconductor memory device (1). The semiconductor memory device (1) of the present embodiment is a volatile memory. As illustrated, the semiconductor memory device (1) includes a memory cell array (11), a raw decoder (12), a sensing amplifier (13), a data control unit (14), a column decoder (15), and a sensing amplifier control unit (16). In addition, the semiconductor memory device (1) includes, in detail as an adjustment unit (20) to be described later, a first comparator (21), a second comparator (22), a zero error counter (23), a one error counter (24), and an error recording unit (25). In addition, the sensing amplifier control unit (16) also functions as one element of the adjustment unit (20). A memory cell array (11) is described using FIG. 2. FIG. 2 is schematically illustrated to explain the memory cell array (11) in detail, and the number or configuration of memory cells is not limited to this; when distinguishing by location, the location is specified and distinguished by attaching [ ]. The memory cell array (11) includes a plurality of memory cells (111) arranged two-dimensionally, corresponding to rows and columns. Memory cells (111) in the same row are connected to the same word line (wl), and memory cells (111) in the same column are connected to the same pair of bit lines (bl) or bit lines (blx). A column line (cl) is connected to the pair of bit lines (bl) and bit lines (blx). Data reading and writing are performed collectively for the plurality of memory cells (111) connected to the same word line (wl). Additionally, the memory cell array (11) includes a plurality of detection amplifiers (13). Multiple detection amplifiers (13) are installed between word lines (wl[i]) to (wl[i+3]) and (wl[j]) to (wl[j+3]). Returning to FIG. 1, the row decoder (12) decodes a row address that specifies the row direction of the memory cell array (11). Then, based on the decoding result, it selects a word line (wl) and applies a voltage required for opening and reading data. Specifically, the row decoder (12) inputs a word line signal (swl) to the memory cell array (11), which activates the word line (wl) selected by the row address information (ar) at a timing specified by the word line start signal (wlon). In addition, address information such as the row address information (ar) and the word line start signal (wlon) are input to each component via a command input/output unit from a memory controller not shown in FIG. 1. When reading data, the detection amplifier (13) detects data read from the memory cell array (11) and transmits it to the data control unit (14). Specifically, the detection amplifier (13) is controlled by the detection amplifier control unit (16), and the detection amplifier control unit (16)