KR-102962542-B1 - THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE, MANUFACTURING METHOD OF THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME

KR102962542B1KR 102962542 B1KR102962542 B1KR 102962542B1KR-102962542-B1

Abstract

A method for manufacturing a three-dimensional semiconductor memory device comprises forming a mold structure on a semiconductor substrate, wherein the mold structure includes insulating films and sacrificial films alternately stacked in a vertical direction, wherein the insulating films expose the ends of the sacrificial films on a connection region of the semiconductor substrate, and the exposed ends of the sacrificial films form a stepped structure on the connection region; forming a sacrificial oxide film covering the exposed ends of the sacrificial films on the mold structure; forming sacrificial pad patterns on the exposed ends of the sacrificial films, respectively; forming a flat insulating film covering the sacrificial oxide film and the sacrificial pad patterns on the mold structure; forming a vertical contact hole penetrating the flat insulating film and penetrating each of the sacrificial pad patterns, wherein the vertical contact hole penetrates the sacrificial oxide film and the mold structure below each of the sacrificial pad patterns; removing each of the sacrificial pad patterns to form a first horizontal recess region; and removing a portion of the sacrificial oxide film exposed by the first horizontal recess region to extend the first horizontal It includes forming a recess area, and forming a cell contact plug that fills the vertical contact hole and the extended first horizontal recess area.

Inventors

손영환
이동근

Assignees

삼성전자주식회사

Dates

Publication Date: 20260511
Application Date: 20211222

Claims (20)

A mold structure is formed on a semiconductor substrate including a cell array region and a connection region, wherein the mold structure includes insulating films and sacrificial films alternately stacked in a vertical direction, the insulating films expose the ends of the sacrificial films on the connection region, and the exposed ends of the sacrificial films form a stepped structure on the connection region; Forming a sacrificial oxide film covering the exposed ends of the sacrificial films on the mold structure; Sacrificial pad patterns are each formed on the exposed ends of the sacrificial films, wherein the sacrificial oxide film is interposed between the exposed ends of the sacrificial films and the sacrificial pad patterns; Forming vertical contact holes that penetrate each of the above sacrificial pad patterns and penetrate the sacrificial oxide film and the mold structure below the above sacrificial pad patterns; Removing the sacrificial pad patterns exposed by the vertical contact holes to form first horizontal recess areas; Recessing the sacrificial membranes exposed by each of the vertical contact holes to form second horizontal recess regions; and Forming blocking patterns that fill the second horizontal recess areas; Removing a portion of the sacrificial oxide film exposed by the first horizontal recess regions to form extended first horizontal recess regions; and Forming a cell contact plug that fills each of the vertical contact holes and each of the extended first horizontal recess regions, comprising: The above first horizontal recess regions are formed on the sacrificial oxide film, and The second horizontal recess regions are formed between the insulating films, and between the uppermost insulating film among the insulating films and the sacrificial oxide film, and A method for manufacturing a three-dimensional semiconductor memory device, wherein the first horizontal recess regions and the second horizontal recess regions are simultaneously formed by a first etching process, and the first etching process includes removing the sacrificial pad patterns and recessing the sacrificial films.
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In claim 1, A method for manufacturing a three-dimensional semiconductor memory device comprising the above-described sacrificial pad patterns, the material having a faster etching rate compared to the above-described sacrificial films.
In claim 1, A method for manufacturing a three-dimensional semiconductor memory device in which the thickness of each of the above-mentioned sacrifice pad patterns along the vertical direction is greater than the thickness of each of the above-mentioned sacrifice films along the vertical direction.
In claim 1, Forming the above blocking patterns is, Forming a blocking film that conformally covers the inner surface of each of the vertical contact holes and the inner surface of each of the first horizontal recess regions, and fills the second horizontal recess regions; and A method for manufacturing a three-dimensional semiconductor memory device comprising removing the blocking film within each of the vertical contact holes and each of the first horizontal recess regions.
In claim 1, Before forming the blocking patterns, forming a blocking film that conformally covers the inner surface of each of the vertical contact holes and the inner surface of each of the first horizontal recess regions, and fills the second horizontal recess regions; Forming a sacrificial polymembrane that fills each remainder of the vertical contact holes and each remainder of the first horizontal recess regions; Forming separation trenches penetrating the above mold structure; Removing the sacrificial films exposed by the above separation trenches to form empty regions between the insulating films; and A method for manufacturing a three-dimensional semiconductor memory device, further comprising forming gate electrodes and horizontal insulating films that fill the above-mentioned empty regions.
In claim 6, Forming separation structures within the above separation trenches, respectively; and A method for manufacturing a three-dimensional semiconductor memory device, further comprising removing the sacrificial polyfilm after the above-mentioned separation structures are formed.
In claim 7, Forming the above blocking patterns is: A method for manufacturing a three-dimensional semiconductor memory device comprising removing the blocking film within each of the vertical contact holes and each of the first horizontal recess regions after the sacrificial polyfilm is removed.
In claim 8, A method for manufacturing a three-dimensional semiconductor memory device, comprising forming the extended first horizontal recess regions, removing portions of the horizontal insulating films exposed by the first horizontal recess regions.
In claim 8, The cell contact plug is formed between the separation structures, and The cell contact plug comprises a vertical portion filling each of the vertical contact holes and a horizontal portion filling each of the extended first horizontal recess areas. A method for manufacturing a three-dimensional semiconductor memory device in which the above horizontal portion is horizontally spaced apart from the above separation structures.
A mold structure is formed on a semiconductor substrate including a cell array region and a connection region, wherein the mold structure includes insulating films and sacrificial films alternately stacked in a vertical direction, the insulating films expose the ends of the sacrificial films on the connection region, and the exposed ends of the sacrificial films form a stepped structure on the connection region; Forming a sacrificial oxide film covering the exposed ends of the sacrificial films on the mold structure; Sacrificial pad patterns are each formed on the exposed ends of the sacrificial films, wherein the sacrificial oxide film is interposed between the exposed ends of the sacrificial films and the sacrificial pad patterns; Forming a flat insulating film covering the sacrificial oxide film and the sacrificial pad patterns on the mold structure; A vertical contact hole is formed that penetrates the flat insulating film and penetrates each of the sacrificial pad patterns, wherein the vertical contact hole penetrates the sacrificial oxide film and the mold structure below each of the sacrificial pad patterns; Each of the above sacrificial pad patterns is removed to form a first horizontal recess area, wherein the first horizontal recess area extends laterally from the vertical contact hole; The above sacrificial membranes are recessed to form second horizontal recess regions, wherein the second horizontal recess regions extend laterally from the vertical contact hole; Forming blocking patterns that fill the second horizontal recess areas; Removing a portion of the sacrificial oxide film exposed by the first horizontal recess region to form an extended first horizontal recess region; and The method comprises forming a cell contact plug that fills the vertical contact hole and the extended first horizontal recess area, wherein The first horizontal recess region is formed on the sacrificial oxide film, and The second horizontal recess regions are formed between the insulating films, and between the uppermost insulating film among the insulating films and the sacrificial oxide film, and A method for manufacturing a three-dimensional semiconductor memory device, wherein the first horizontal recess region and the second horizontal recess region are simultaneously formed by a first etching process, and the first etching process includes removing each of the sacrificial pad patterns and recessing the sacrificial films.
In claim 11, A method for manufacturing a three-dimensional semiconductor memory device in which the thickness of each of the above-mentioned sacrifice pad patterns along the vertical direction is greater than the thickness of each of the above-mentioned sacrifice films along the vertical direction.
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In claim 11, Before forming the above blocking patterns, forming a blocking film that conformally covers the inner surface of the vertical contact hole and the inner surface of the first horizontal recess area and fills the second horizontal recess areas; Forming a sacrificial polymembrane that fills the remainder of the vertical contact hole and the remainder of the first horizontal recess area; Forming separation trenches penetrating the above mold structure; Removing the sacrificial films exposed by the above separation trenches to form empty regions between the insulating films; and A method for manufacturing a three-dimensional semiconductor memory device, further comprising forming gate electrodes and horizontal insulating films that fill the above-mentioned empty regions.
In claim 14, Forming separation structures within the above separation trenches, respectively; Removing the above sacrificial polymembrane; and A method for manufacturing a three-dimensional semiconductor memory device further comprising forming the blocking patterns locally provided within the second horizontal recess regions.
In claim 15, Forming the above blocking patterns includes removing the blocking film within the vertical contact hole and the first horizontal recess area, and A method for manufacturing a three-dimensional semiconductor memory device in which portions of the blocking film filling the second horizontal recess regions constitute the blocking patterns.
In claim 16, Forming the extended first horizontal recess region comprises removing a portion of a corresponding horizontal insulating film among the horizontal insulating films exposed by the first horizontal recess region, and A method for manufacturing a three-dimensional semiconductor memory device in which the above-mentioned extended first horizontal recess region exposes the upper surface of the pad portion of a corresponding gate electrode among the gate electrodes.
In claim 11, Removing the sacrificial membranes to form empty regions within the mold structure; and Further comprising forming gate electrodes and horizontal insulating films that fill the above empty regions, The above-mentioned extended first horizontal recess region exposes the upper surface of the pad portion of the corresponding gate electrode among the gate electrodes, and The cell contact plug includes a vertical portion that fills the vertical contact hole and a horizontal portion that fills the extended first horizontal recess area. A method for manufacturing a three-dimensional semiconductor memory device in which the bottom surface of the horizontal portion is vertically joined to the upper surface of the pad portion of the corresponding gate electrode.
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Description

Three-dimensional semiconductor memory device, manufacturing method of the same, and electronic system including the same The present invention relates to a three-dimensional semiconductor memory device, a method for manufacturing the same, and an electronic system including the same, and more specifically, to a non-volatile three-dimensional semiconductor memory device including a vertical channel, a method for manufacturing the same, and an electronic system including the same. In electronic systems requiring data storage, there is a demand for semiconductor devices capable of storing high-capacity data. To increase data storage capacity while meeting the superior performance and low cost demands of consumers, it is necessary to increase the integration density of semiconductor devices. In the case of two-dimensional or planar semiconductor devices, integration density is primarily determined by the area occupied by a unit memory cell, and thus is significantly influenced by the level of fine pattern formation technology. However, since ultra-expensive equipment is required for pattern miniaturization, the increase in integration density of two-dimensional semiconductor devices is limited. Accordingly, three-dimensional semiconductor memory devices equipped with memory cells arranged in three dimensions are being proposed. FIG. 1 is a schematic diagram illustrating an electronic system including a three-dimensional semiconductor memory device according to embodiments of the present invention. FIG. 2 is a schematic perspective view showing an electronic system including a three-dimensional semiconductor memory device according to embodiments of the present invention. FIGS. 3 and FIGS. 4 are cross-sectional views for illustrating a semiconductor package including a three-dimensional semiconductor memory device according to embodiments of the present invention, corresponding respectively to cross-sections of FIG. 2 cut along the lines II' and II-II'. FIG. 5 is a plan view for illustrating a three-dimensional semiconductor memory device according to embodiments of the present invention. Figure 6a is a cross-sectional view taken along the line A-A' of Figure 5, and Figure 6b is a cross-sectional view taken along BB' and C-C' of Figure 5. Figure 7a is an enlarged view of part P1 of Figure 6b, and Figure 7b is an enlarged view of part P2 of Figure 6b. FIGS. 8a to 15a are drawings for explaining a method for manufacturing a three-dimensional semiconductor memory device according to embodiments of the present invention, and are cross-sectional views corresponding to A-A' of FIG. 5. FIGS. 8b to 15b are drawings for explaining a method for manufacturing a three-dimensional semiconductor memory device according to embodiments of the present invention, and are cross-sectional views corresponding to BB' and C-C' of FIG. 5. FIG. 16 is a drawing showing a three-dimensional semiconductor memory device according to embodiments of the present invention, and is a cross-sectional view corresponding to line A-A' of FIG. 5. FIG. 17 is a drawing showing a three-dimensional semiconductor memory device according to embodiments of the present invention, and is a cross-sectional view corresponding to line A-A' of FIG. 5. The present invention will be described in detail below by explaining exemplary embodiments of the invention with reference to the attached drawings. FIG. 1 is a schematic diagram illustrating an electronic system including a three-dimensional semiconductor memory device according to embodiments of the present invention. Referring to FIG. 1, an electronic system (1000) according to embodiments of the present invention may include a three-dimensional semiconductor memory device (1100) and a controller (1200) electrically connected to the three-dimensional semiconductor memory device (1100). The electronic system (1000) may be a storage device comprising one or more three-dimensional semiconductor memory devices (1100) or an electronic device comprising said storage device. As an example, the electronic system (1000) may be a solid state drive device (SSD), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device comprising one or more three-dimensional semiconductor memory devices (1100). The three-dimensional semiconductor memory device (1100) may be a non-volatile memory device and, as an example, may be a three-dimensional NAND flash memory device as described below. The three-dimensional semiconductor memory device (1100) may include a first region (1100F) and a second region (1100S) on the first region (1100F). According to some embodiments, the first region (1100F) may be positioned next to the second region (1100S) as shown. The first region (1100F) may be a peripheral circuit region including a decoder circuit (1110), a page buffer (1120), and a logic circuit (1130). The second region (1100S) may be a memory cell region comprising a bit line (BL), a common source line (CSL