KR-102962639-B1 - SCAN DRIVER AND DISPLAY DEVICE

KR102962639B1KR 102962639 B1KR102962639 B1KR 102962639B1KR-102962639-B1

Abstract

The scanning driving unit includes a plurality of stages. Each of the stages includes an input unit that controls a first node and a second node based on signals supplied to a first input terminal and a second input terminal; a first signal processing unit that supplies the voltage of a second power source to a fourth node based on the voltage of the first node, or electrically connects the second node and the fourth node through a fifth node based on the voltage of the first power source; a second signal processing unit that includes a first transistor connected between a third node and a sixth node, is connected to the first input terminal, the second input terminal, and the first power source, and controls the third node based on the operation of the first transistor; and an output unit that controls the voltage applied to the third node to be less than or equal to the voltage of the first power source, and supplies the voltage of the first power source or the voltage of the second power source to an output terminal as a scanning signal based on the voltage of the third node and the voltage of the fourth node.

Inventors

권순기
인해정

Assignees

삼성디스플레이 주식회사

Dates

Publication Date: 20260511
Application Date: 20250710

Claims (14)

It includes multiple stages, Each of the above stages is, An input unit that controls a first node and a second node based on signals supplied to a first input terminal and a second input terminal; A first signal processing unit that supplies the voltage of a second power source to a fourth node based on the voltage of the first node, or electrically connects the second node and the fourth node through a fifth node based on the voltage of the first power source; A second signal processing unit comprising a first transistor connected between a third node and a sixth node, connected to the first input terminal, the second input terminal and the first power supply, and controlling the third node based on the operation of the first transistor; and A scanning driving unit comprising an output unit that controls the voltage applied to the third node to be less than or equal to the voltage of the first power source, and supplies the voltage of the first power source or the voltage of the second power source as a scanning signal to an output terminal based on the voltage of the third node and the voltage of the fourth node.
In paragraph 1, the output unit is, A second transistor connected between the second power source and the output terminal, wherein the gate electrode receives the voltage of the fourth node; and A scanning driving unit comprising a third transistor connected between the output terminal and the first power source, wherein the gate electrode receives the voltage of the third node.
In paragraph 1, the input unit is, A fourth transistor connected between the first input terminal and the first node, with its gate electrode connected to the second input terminal to receive a first clock signal; A fifth transistor connected between the first node and the second node, wherein the gate electrode receives the voltage of the first node; and A scanning driver comprising a sixth transistor connected to the second node and the first power source, with the gate electrode connected to the second input terminal to receive the first clock signal.
In paragraph 1, the first signal processing unit is, A second capacitor, one end of which is connected to the fifth node and the other end of which is connected to the first electrode of the eighth transistor; A seventh transistor connected between the first electrode and the third input terminal of the eighth transistor, wherein the gate electrode receives the voltage of the fifth node; The eighth transistor connected between the first electrode of the seventh transistor and the fourth node, and having a gate electrode that receives a second clock signal output from the third input terminal; A first capacitor, one end of which is connected to the fourth node and the other end of which is connected to the second power source; A ninth transistor connected to the fourth node and the second power source, with a gate electrode receiving the voltage of the first node; and A scanning driver comprising a 10th transistor connected to the first node and the second power source, with the gate electrode connected to a reset input terminal.
In paragraph 1, the second signal processing unit is, A 11th transistor connected between the 1st input terminal and the 12th transistor, wherein the gate electrode receives a 1st clock signal output from the 2nd input terminal; The 12th transistor connected between the 11th transistor and the 6th node, wherein the gate electrode receives the voltage of the 1st power supply; A 13th transistor connected between a 3rd input terminal and a 7th node, wherein the gate electrode receives the voltage of the 6th node; A third capacitor, one end of which is connected to the sixth node and the other end of which is connected to the seventh node; and A scanning driver comprising a 14th transistor connected to the 7th node and the 2nd power source, wherein the gate electrode receives the voltage of the 2nd node.
In paragraph 1, A scanning drive unit further comprising a stabilization unit electrically connected between the input unit and the output unit, and limiting the voltage drop of the first node and the voltage drop of the second node.
In paragraph 6, the above-mentioned stabilization part is, A 15th transistor connected between the 2nd node and the 5th node, wherein the gate electrode receives the voltage of the 1st power source; and A scanning drive unit comprising a 16th transistor connected between the first node and the third node, wherein the gate electrode receives the voltage of the first power source.
Multiple pixels; and It includes a scanning drive unit comprising a plurality of stages, and Each of the above plurality of pixels is, Light-emitting element; A first pixel transistor connected between a first pixel node and a third pixel node, with its gate electrode connected to a second pixel node; A second pixel transistor connected between a data line and the first pixel node, with a gate electrode connected to the i-th (i is a natural number greater than or equal to 2)-th first scan line; A third pixel transistor connected between the third pixel node and the second pixel node, with its gate electrode connected to the i-th second scan line; A fourth pixel transistor connected between the second pixel node and the first initialization power supply, with its gate electrode connected to the i-1th second scan line; A fifth pixel transistor connected between a first driving power source and the first pixel node, with its gate electrode connected to the i-th light emission control line; A sixth pixel transistor connected between the third pixel node and the fourth pixel node, with its gate electrode connected to the i-th light emission control line; A seventh pixel transistor connected between the fourth pixel node and the second initialization power supply, with its gate electrode connected to the i-th first scan line; and It includes a storage capacitor connected between the first driving power source and the second pixel node, and Each of the above stages is, An input unit that controls a first node and a second node based on signals supplied to a first input terminal and a second input terminal; A first signal processing unit that supplies the voltage of a second power source to a fourth node based on the voltage of the first node, or electrically connects the second node and the fourth node through a fifth node based on the voltage of the first power source; A second signal processing unit comprising a first transistor connected between a third node and a sixth node, connected to the first input terminal, the second input terminal and the first power supply, and controlling the third node based on the operation of the first transistor; and A display device comprising an output unit that controls the voltage applied to the third node to be less than or equal to the voltage of the first power source, and supplies the voltage of the first power source or the voltage of the second power source as a scan signal to an output terminal based on the voltage of the third node and the voltage of the fourth node.
In paragraph 8, the above output unit is, A second transistor connected between the second power source and the output terminal, wherein the gate electrode receives the voltage of the fourth node; and A display device comprising a third transistor connected between the output terminal and the first power source, wherein the gate electrode receives the voltage of the third node.
In paragraph 8, the above input unit is, A fourth transistor connected between the first input terminal and the first node, with its gate electrode connected to the second input terminal to receive a first clock signal; A fifth transistor connected between the first node and the second node, wherein the gate electrode receives the voltage of the first node; and A display device comprising a sixth transistor connected to the second node and the first power source, with the gate electrode connected to the second input terminal to receive the first clock signal.
In paragraph 8, the first signal processing unit is, A second capacitor, one end of which is connected to the fifth node and the other end of which is connected to the first electrode of the eighth transistor; A seventh transistor connected between the first electrode and the third input terminal of the eighth transistor, wherein the gate electrode receives the voltage of the fifth node; The eighth transistor connected between the first electrode of the seventh transistor and the fourth node, and having a gate electrode that receives a second clock signal output from the third input terminal; A first capacitor, one end of which is connected to the fourth node and the other end of which is connected to the second power source; A ninth transistor connected to the fourth node and the second power source, with a gate electrode receiving the voltage of the first node; and A display device comprising a 10th transistor connected to the first node and the second power source, with the gate electrode connected to a reset input terminal.
In paragraph 8, the second signal processing unit is, A 11th transistor connected between the 1st input terminal and the 12th transistor, wherein the gate electrode receives a 1st clock signal output from the 2nd input terminal; The 12th transistor connected between the 11th transistor and the 6th node, wherein the gate electrode receives the voltage of the 1st power supply; A 13th transistor connected between a 3rd input terminal and a 7th node, wherein the gate electrode receives the voltage of the 6th node; A third capacitor, one end of which is connected to the sixth node and the other end of which is connected to the seventh node; and A display device comprising a 14th transistor connected to the 7th node and the 2nd power source, wherein the gate electrode receives the voltage of the 2nd node.
In paragraph 8, A display device further comprising a stabilization unit electrically connected between the input unit and the output unit, and limiting the voltage drop of the first node and the voltage drop of the second node.
In Clause 13, the above-mentioned stabilization part is, A 15th transistor connected between the 2nd node and the 5th node, wherein the gate electrode receives the voltage of the 1st power source; and A display device comprising a 16th transistor connected between the first node and the third node, wherein the gate electrode receives the voltage of the first power source.

Description

Scan Driver and Display Device The embodiment relates to an injection drive unit and a driving method thereof, and more specifically, to an injection drive unit and a driving method thereof for reducing power consumption by maintaining the output voltage of the injection drive unit constant. Generally, a display device comprises a data driver for supplying a data signal to data lines, a scanning driver for supplying a scanning signal to scanning lines, a light-emitting driver for supplying a light-emitting control signal to a light-emitting control line, and pixels positioned to be connected to the data lines, scanning lines, and light-emitting control lines. Conventionally, in order to reduce the power consumption of the display device, the scanning drive unit was driven by reducing the frequency from the existing standardized fixed frequency driving method. However, when the driving frequency of the scanning driver is reduced to decrease power consumption, the clock signal input to the scanning driver during the hold period when a start pulse is not input is maintained at a fast frequency. FIG. 1 is a drawing illustrating a display device according to an embodiment. FIG. 2 is a circuit diagram showing an example of a pixel included in the display device of FIG. 1 according to an embodiment. FIG. 3 is a timing diagram showing the driving of the pixel of FIG. 2 according to an embodiment. FIG. 4 is a block diagram illustrating an injection driving unit according to an embodiment. FIG. 5 is a timing diagram illustrating a scanning signal output from a scanning driving unit included in a display device according to an embodiment. FIG. 6 is a circuit diagram showing an example of a stage included in the scanning drive unit of FIG. 4 according to an embodiment. Figure 7 is a timing diagram showing the stage operation of Figure 6. FIG. 8 is a circuit diagram showing another embodiment of the stage according to the embodiment of FIG. 6. FIG. 9a is a circuit diagram showing an example of a stage included in the scanning drive unit of FIG. 4 according to another embodiment. Fig. 9b is a timing diagram showing the stage operation of Fig. 9a. FIG. 9c is a circuit diagram showing another embodiment of the stage according to the embodiment of FIG. 9a. Preferred embodiments are described in detail below with reference to the attached drawings. The advantages and features of the embodiments and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the attached drawings. However, the embodiments disclosed below are not limited to those described below and may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the invention is complete and to fully inform those skilled in the art of the scope of the invention, and the embodiments are defined only by the scope of the claims. Throughout the specification, the same reference numerals refer to the same components. Unless otherwise defined, all terms used herein (including technical and scientific terms) may be used in a meaning commonly understood by those skilled in the art to which the embodiments pertain. Additionally, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise. The terms used herein are intended to describe the embodiments and are not intended to limit the embodiments. In this specification, the singular form includes the plural form unless specifically stated otherwise in the text. Hereinafter, a display device according to an embodiment will be described with reference to FIG. 1. FIG. 1 is a drawing illustrating a display device according to an embodiment. The display device (1000) may include a display unit (100), a first scanning drive unit (200), a second scanning drive unit (300), a light-emitting drive unit (400), a data drive unit (500), and a timing control unit (600). The display device (1000) can display images at various driving frequencies (or image refresh rates, screen refresh rates) depending on driving conditions. At this time, the driving frequency is the frequency at which a data signal is substantially written to the driving transistor of a pixel (PX). Specifically, the driving frequency is called the screen refresh rate or screen refresh frequency, and refers to the frequency at which the display screen is refreshed per second. For example, the display device (1000) can display images corresponding to various driving frequencies from 1 Hz to 120 Hz. The display unit (100) displays an image. The display unit (100) has pixels (PX) positioned to be connected to data lines (D), scan lines (S1, S2), and light emission control lines (E). At this time, the pixels (PX) can receive voltages of a first driving power supply (VDD), a second driving power supply (VSS), and an initialization power supply (Vint) from the outside. Addition