KR-102962672-B1 - Storage device and storage system including the same

Abstract

A storage device and a storage system including the same are disclosed. A storage device according to the technical concept of the present disclosure includes a reference clock pin configured to receive a reference clock from a host, a reference clock frequency discriminator configured to determine a reference clock frequency from a reference clock received through the reference clock pin, and a device controller configured to perform link startup in a high-speed mode between a host and a storage device according to the determined reference clock frequency.

Inventors

• 노관우
• 서성호
• 정용우
• 남동우
• 신명섭
• 장현규

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260508

Application Date

20201005

Priority Date

20200220

Claims (20)

1. As a storage device, Reference clock pin configured to receive a reference clock from a host; A reference clock frequency discriminator configured to determine the reference clock frequency from the reference clock received through the reference clock pin; and It includes a device controller configured to perform a link startup in high-speed mode between the host and the storage device according to the determined reference clock frequency, and The above reference clock frequency discriminator is, A first RC filter that generates a first output voltage corresponding to the reference clock at a first time point; A second RC filter that generates a second output voltage corresponding to the reference clock at a second time point different from the first time point; and It includes a divider connected between the reference clock pin and the first and second RC filters, and generating a divided reference clock by dividing the reference clock. The above reference clock frequency discriminator determines the reference clock frequency based on the first and second output voltages, and The first RC filter generates the first output voltage from the divided reference clock at the first time point corresponding to the first time constant, and A storage device characterized in that the second RC filter generates the second output voltage from the divided reference clock at the second time point corresponding to the second time constant.
2. In paragraph 1, the storage device is, A storage device characterized by receiving the reference clock from the host through the reference clock pin during the initialization or booting phase of the storage device.
3. In paragraph 1, An input signal pin configured to receive an input signal from the above host; and It further includes an interconnect section connected to the input signal pin and configured to transmit and receive data with the host, A storage device characterized by the above device controller setting the physical layer of the interconnect section according to the determined reference clock frequency.
4. In paragraph 3, A storage device characterized by the above reference clock frequency discriminator transmitting the discriminated reference clock frequency to the link layer of the above interconnect section.
5. In paragraph 3, A storage device characterized in that the above reference clock frequency discriminator is included in the above interconnect section.
6. In paragraph 1, A storage device characterized in that the above reference clock frequency discriminator is included in the above device controller.
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10. In paragraph 1, the reference clock frequency discriminator is, A first monitor signal generator that generates a first monitor signal enabled according to the voltage level of the first output voltage at the first time point; A second monitor signal generator that generates a second monitor signal enabled according to the voltage level of the second output voltage at the second time point; and A storage device characterized by further including a discriminator that determines the reference clock frequency based on the first and second monitor signals.
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12. In paragraph 1, A storage device characterized by being a UFS device that is interconnected with the host via the Universal Flash Storage (UFS) standard.
13. As a storage device, Reference clock pin configured to receive a reference clock from a host; A reference clock frequency discriminator configured to determine the reference clock frequency from the reference clock received through the reference clock pin; and The device controller includes a device controller configured to dynamically change the speed gear between the host and the storage device according to the changed second reference clock frequency when the reference clock frequency changes from a first reference clock frequency to a second reference clock frequency in a linkup state between the host and the storage device. The above reference clock frequency discriminator is, A first RC filter that generates a first output voltage corresponding to the reference clock at a first time point; A second RC filter that generates a second output voltage corresponding to the reference clock at a second time point different from the first time point; and It includes a divider connected between the reference clock pin and the first and second RC filters, and generating a divided reference clock by dividing the reference clock. The above reference clock frequency discriminator determines the reference clock frequency based on the first and second output voltages, and The first RC filter generates the first output voltage from the divided reference clock at the first time point corresponding to the first time constant, and A storage device characterized in that the second RC filter generates the second output voltage from the divided reference clock at the second time point corresponding to the second time constant.
14. In Paragraph 13, An input signal pin configured to receive an input signal from the above host; and It further includes an interconnect section connected to the input signal pin and configured to transmit and receive data with the host, A storage device characterized by the above device controller setting the physical layer of the interconnect section according to the first reference clock frequency and resetting the physical layer of the interconnect section according to the second reference clock frequency.
15. In Clause 14, the above reference clock frequency discriminator is, The above first reference clock frequency is transmitted to the link layer of the interconnect section, and A storage device characterized by transmitting the above second reference clock frequency to the link layer of the above interconnect section.
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18. As a storage device, Reference clock pin configured to receive a reference clock from a host; A reference clock detector that detects whether the reference clock is received through the reference clock pin; A device controller configured to perform link startup in high-speed mode between the host and the storage device when the reference clock is received through the reference clock pin during the initialization or booting phase of the storage device; and It includes a reference clock frequency discriminator configured to determine the reference clock frequency from the reference clock received through the reference clock pin, and The above reference clock frequency discriminator is, A first RC filter that generates a first output voltage corresponding to the reference clock at a first time point; A second RC filter that generates a second output voltage corresponding to the reference clock at a second time point different from the first time point; and It includes a divider connected between the reference clock pin and the first and second RC filters, and generating a divided reference clock by dividing the reference clock. The above reference clock frequency discriminator determines the reference clock frequency based on the first and second output voltages, and The first RC filter generates the first output voltage from the divided reference clock at the first time point corresponding to the first time constant, and A storage device characterized in that the second RC filter generates the second output voltage from the divided reference clock at the second time point corresponding to the second time constant.
19. In paragraph 18, the above reference clock detector is, An RC filter that generates an output voltage corresponding to the reference clock at a first point in time; A monitor signal generator that generates a monitor signal enabled according to the voltage level of the output voltage at the first time point; and A storage device characterized by including a detector that detects whether the reference clock is toggled based on the above monitor signal.
20. In Paragraph 18, A storage device characterized in that the above device controller is configured to perform the link startup in the high-speed mode between the host and the storage device according to the determined reference clock frequency.

Description

Storage device and storage system including the same The technical concept of the present disclosure relates to a memory device, and more specifically, to a storage device and a storage system including the same. A storage system consists of a host and a storage device. The host and the storage device are connected via various standard interfaces such as UFS (universal flash storage), SATA (serial ATA), SCSI (small computer small interface), SAS (serial attached SCSI), and eMMC (embedded MMC). When a storage system is used in a mobile device, high-speed operation between the host and the storage device is critical, and rapid link-up between the host and the storage device is required. FIG. 1 is a block diagram showing a storage system according to one embodiment of the present disclosure. FIG. 2 shows an interface between a host and a storage device according to one embodiment of the present disclosure. FIG. 3 is a block diagram showing a storage system according to one embodiment of the present disclosure. FIG. 4 is a block diagram showing a reference clock frequency counter according to one embodiment of the present disclosure. FIG. 5 is a timing diagram exemplarily illustrating the counting operation of the reference clock frequency counter of FIG. 4 according to one embodiment of the present disclosure. FIG. 6 is a block diagram showing a reference clock frequency discriminator according to one embodiment of the present disclosure. FIG. 7 is a block diagram showing a reference clock frequency discriminator according to one embodiment of the present disclosure. FIG. 8 is a timing diagram exemplarily illustrating the frequency determination operation of the reference clock frequency discriminator of FIG. 7 according to one embodiment of the present disclosure. FIG. 9 is a flowchart illustrating a method of operation of a storage device according to one embodiment of the present disclosure. FIG. 10 is a flowchart illustrating the operation between a host and a storage device according to one embodiment of the present disclosure. FIG. 11 is a flowchart illustrating a method of operation of a storage device according to one embodiment of the present disclosure. FIG. 12 is a flowchart exemplarily illustrating a high-speed mode initialization sequence between a UFS host and a UFS device according to one embodiment of the present disclosure. FIG. 13 is a block diagram showing a reference clock detector according to one embodiment of the present disclosure. FIG. 14 is a timing diagram exemplarily illustrating the reference clock detection operation of the reference clock detector of FIG. 13 according to one embodiment of the present disclosure. FIGS. 15 to 17 are flowcharts illustrating methods of operation of a storage device according to some embodiments of the present disclosure, respectively. FIG. 18 exemplarily illustrates the reference clock frequency update operation of a reference clock frequency discriminator according to one embodiment of the present disclosure. FIG. 19 is a flowchart illustrating the operation between a host and a storage device according to one embodiment of the present disclosure. FIG. 20 is a block diagram showing a storage system according to one embodiment of the present disclosure. FIGS. 21 to 23 are tables showing control signals according to some embodiments of the present disclosure, respectively. FIG. 24 is a drawing for explaining a UFS system according to one embodiment of the present invention. FIGS. 25a to 25c are drawings for explaining the form factor of a UFS card. FIG. 26 is a block diagram showing a memory system according to one embodiment of the present disclosure. FIG. 27 is a drawing for explaining a 3D VNAND structure that can be applied to a UFS device according to one embodiment of the present disclosure. FIG. 28 is a drawing for explaining a BVNAND structure that can be applied to a UFS device according to one embodiment of the present disclosure. Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. FIG. 1 is a block diagram showing a storage system (10) according to one embodiment of the present disclosure. Referring to FIG. 1, the storage system (10) includes a storage device (100) and a host (200). For example, the storage device (100) and the host (200) may be connected according to an interface protocol defined in the Universal Flash Storage (UFS) standard, and accordingly, the storage device (100) may be a UFS device and the host (200) may be a UFS host. However, the present invention is not limited thereto, and the storage device (100) and the host (200) may be connected according to various standard interfaces. The host (200) can control data processing operations for the storage device (100), such as data reading operations or data writing operations. The host (200) may refer to a data processing device capable of processing data, such as a CPU (Central Processing Unit), a processor,