KR-102962673-B1 - Link startup method of storage device

Abstract

A storage device that performs high-speed link startup and a storage system including the same are disclosed. A link startup method of a storage device according to the technical concept of the present disclosure receives a line-reset signal from a host through a line connected to an input signal pin of the storage device, compares the length of the received line-reset signal with a first reference time, and performs a link startup operation between the storage device and the host in a high-speed mode or a low-speed mode according to the result of the comparison.

Inventors

• 서성호
• 노관우
• 신명섭
• 남동우

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260508

Application Date

20201021

Priority Date

20200427

Claims (20)

1. As a method for link startup of a storage device, A step of receiving a line-reset signal from a host through a line connected to an input signal pin of the storage device; A step of comparing the length of the received line-reset signal with a first reference time; and A method comprising the step of performing a link startup operation in a high-speed mode or a low-speed mode between the storage device and the host according to the above comparison result.
2. In paragraph 1, the step of performing the link startup operation is, If the length of the line-reset signal is shorter than the first reference time, the step of performing the link startup operation in the high-speed mode; and A method comprising the step of performing the link startup operation in the low-speed mode when the length of the line-reset signal is not shorter than the first reference time.
3. In claim 1, the step of receiving the line-reset signal is The method includes the step of receiving a line-reset signal from the host, wherein the line has a positive differential line voltage. The step of comparing the length of the line-reset signal with the first reference time is A method characterized by including the step of comparing the length of a line-reset interval having the positive differential line voltage of the above line with the first reference time.
4. In paragraph 3, The above input signal pin includes a positive input signal pin configured to receive a positive input signal and a negative input signal pin configured to receive a negative input signal, and The above line includes a positive line connected to the positive input signal pin and a negative line connected to the negative input signal pin, and A method characterized by receiving the line-reset signal, wherein the voltage of the positive line is higher than the voltage of the negative line.
5. In paragraph 4, The step of comparing the length of the line-reset signal with the first reference time is A step of generating a differential line voltage by comparing the voltage of the positive line and the voltage of the negative line; A step of generating a system clock count value by counting the number of clocks in the system clock; and A method characterized by including the step of determining the length of the line-reset signal based on the differential line voltage and the system clock count value.
6. In paragraph 1, The step of comparing the length of the line-reset signal with the first reference time is A step of detecting an output voltage corresponding to the differential line voltage of the line at a first time point using an RC filter having a time constant corresponding to the first reference time; and A method comprising the step of generating a trigger signal based on the detected output voltage.
7. In paragraph 1, A method characterized in that the first reference time is approximately 300 μs.
8. In paragraph 1, A method comprising, before the step of comparing the length of the line-reset signal above with the first reference time, an additional step of comparing the length of the received line-reset signal with a second reference time smaller than the first reference time.
9. In paragraph 8, the step of performing the above link startup operation is, If the length of the line-reset signal is longer than the second reference time and shorter than the first reference time, the step of performing the link startup operation in the high-speed mode; and A method comprising the step of performing the link startup operation in the low-speed mode when the length of the line-reset signal is not shorter than the first reference time.
10. In paragraph 8, A method characterized in that the second reference time is approximately 200 μs.
11. In paragraph 1, The storage device includes an interconnect section configured to transmit and receive data with the host, and The above method is, A method characterized by further including the step of setting the physical layer or link layer of the interconnect part according to the above comparison result.
12. In claim 1, the step of receiving the line-reset signal is A method comprising the step of the above line transitioning from a negative differential line voltage to a positive differential line voltage.
13. In Paragraph 12, The storage device includes an interconnect section configured to transmit and receive data with the host, and The above method is, Before the step of comparing the length of the line-reset signal with the first reference time, the step of comparing the activation interval in which the line has the negative differential line voltage with the third reference time; and A method characterized by further including the step of setting the physical layer or link layer of the interconnect section when the activation period is shorter than the third reference time.
14. In paragraph 1, A method comprising, prior to the step of receiving the above line-reset signal, an additional step of escaping the power-saving hibernate state (HIBERN8).
15. In paragraph 1, A method characterized in that the storage device is a UFS device interconnected with the host via the Universal Flash Storage (UFS) standard.
16. As a method for link startup of a storage device, A step of determining whether a line-reset signal is received from a host through a line connected to an input signal pin of the storage device; When the line-reset signal is received from the host, the step of performing a high-speed mode link startup operation between the storage device and the host; and A method comprising the step of performing a low-speed mode link startup operation between the storage device and the host when the line-reset signal is not received from the host.
17. In Paragraph 16, The step of determining whether the above line-reset signal is received is: A method characterized by including a step of determining whether the above line has a line-reset section having a positive differential line voltage.
18. As a method for link startup of a storage device, A step of performing a high-speed mode link startup operation between the storage device and the host; A step of determining whether the above high-speed mode link startup operation is completed; When the above high-speed mode link startup operation is completed, a step of determining whether the link up between the storage device and the host has been passed; and A method comprising the step of performing a low-speed mode link startup operation between the storage device and the host when the above link-up is not passed.
19. In Paragraph 18, The step of determining whether the above high-speed mode link startup operation is completed is: A method characterized by including a step of determining whether a threshold time has elapsed from the start time of the above high-speed mode link startup operation.
20. In Paragraph 18, The step of determining whether the above link-up has passed is, A method characterized by including a step of determining whether performance information has been received from the above host.

Description

Link startup method of storage device The technical concept of the present disclosure relates to a memory device, and more specifically, to a link startup method for a storage device and a storage device for performing high-speed link startup. A storage system consists of a host and a storage device. The host and the storage device are connected via various standard interfaces such as UFS (universal flash storage), SATA (serial ATA), SCSI (small computer small interface), SAS (serial attached SCSI), and eMMC (embedded MMC). When a storage system is used in a mobile device, high-speed operation between the host and the storage device is critical, and rapid link-up between the host and the storage device is required. FIG. 1 is a block diagram showing a storage system according to one embodiment of the present disclosure. FIG. 2 shows an interface between a host and a storage device according to one embodiment of the present disclosure. FIG. 3 is a timing diagram showing a line-reset signal according to one embodiment of the present disclosure. FIG. 4 is a table showing line-reset parameters and line-reset high-speed link-up parameters according to one embodiment of the present disclosure. FIG. 5 is a block diagram showing a storage system according to one embodiment of the present disclosure. FIG. 6 is a block diagram showing a line-reset detector according to one embodiment of the present disclosure. FIG. 7 is a timing diagram exemplarily illustrating the detection operation of the line-reset detector of FIG. 6 according to one embodiment of the present disclosure. FIG. 8 is a block diagram showing a line-reset detector according to one embodiment of the present disclosure. FIG. 9 is a block diagram showing a line-reset detector according to one embodiment of the present disclosure. FIG. 10 is a timing diagram exemplarily illustrating the detection operation of the line-reset detector of FIG. 9 according to one embodiment of the present disclosure. FIG. 11 is a flowchart illustrating a method of operation of a storage device according to one embodiment of the present disclosure. FIG. 12 is a flowchart illustrating the operation between a host and a storage device according to one embodiment of the present disclosure. FIG. 13 is a flowchart illustrating a method of operation of a storage device according to one embodiment of the present disclosure. FIG. 14 is a flowchart exemplarily illustrating a high-speed mode initialization sequence between a UFS host and a UFS device according to one embodiment of the present disclosure. FIG. 15 is a flowchart illustrating a link startup operation between a host and a storage device according to one embodiment of the present disclosure. FIGS. 16 to 18 are flowcharts illustrating a link startup method of a storage device according to some embodiments of the present disclosure, respectively. FIG. 19 is a flowchart illustrating a link startup operation between a host and a storage device according to one embodiment of the present disclosure. FIGS. 20 and FIGS. 21 are flowcharts illustrating a link startup method of a storage device according to some embodiments of the present disclosure, respectively. FIG. 22 is a flowchart illustrating the operation between a host and a storage device according to one embodiment of the present disclosure. FIGS. 23 and FIGS. 24 are flowcharts illustrating a link startup method of a storage device according to some embodiments of the present disclosure, respectively. FIG. 25 is a drawing for explaining a UFS system according to one embodiment of the present invention. FIGS. 26a to 26c are drawings for explaining the form factor of a UFS card. FIG. 27 is a block diagram showing a memory system according to one embodiment of the present disclosure. FIG. 28 is a drawing for explaining a 3D VNAND structure that can be applied to a UFS device according to one embodiment of the present disclosure. FIG. 29 is a drawing for explaining a BVNAND structure that can be applied to a UFS device according to one embodiment of the present disclosure. Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. FIG. 1 is a block diagram showing a storage system (10) according to one embodiment of the present disclosure. Referring to FIG. 1, the storage system (10) includes a storage device (100) and a host (200). For example, the storage device (100) and the host (200) may be connected according to an interface protocol defined in the Universal Flash Storage (UFS) standard, and accordingly, the storage device (100) may be a UFS device and the host (200) may be a UFS host. However, the present invention is not limited thereto, and the storage device (100) and the host (200) may be connected according to various standard interfaces. The host (200) may include an interconnect section (210) and a host controller (220). The host (200) may control data processing operations for the storage device (100), suc