KR-102962674-B1 - AN OPERATING METHOD OF HOST DEVICE AND STORAGE DEVICE USING A CREDIT

Abstract

An electronic device according to the technical concept of the present disclosure may be characterized by connecting a host device and a storage device according to the Universal Flash Storage standard, wherein the host device comprises at least one core configured to process a submission queue (SQ), which is a processing queue for commands, and a completion queue (CQ), which is a processing queue for responses received from the storage device; a host controller configured to transmit the commands to the storage device; a host command register configured to store a host command credit indicating an estimated acceptance limit for the commands of the storage device; a response slot configured to store the responses; and a host response register configured to store a host response credit indicating a limit of the response slot.

Inventors

• 신명섭
• 서성호
• 장성용
• 정해성

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20201012

Claims (20)

1. In an electronic device that connects a host device and a storage device using the Universal Flash Storage standard, The above host device is, At least one core configured to process a submission queue (SQ), which is a processing queue for commands, and a completion queue (CQ), which is a processing queue for responses received from the storage device; A host controller configured to transmit the above command to the storage device; A host command register configured to store a host command credit indicating an estimated acceptance limit for the command of the storage device; A response slot configured to store the above response; and An electronic device characterized by including a host response register configured to store a host response credit indicating the limit of the above response slot.
2. In paragraph 1, The above host controller is, An electronic device characterized by checking for empty space in a command slot included in the storage device based on the above host command credit, and transmitting the command and the host response credit to the storage device.
3. In paragraph 1, The above storage device is, A storage response register configured to store a storage response credit indicating an estimated acceptance limit for the response of the host device; A command slot configured to store the above command; A storage command register configured to store a storage command credit indicating the limit of the above command slot; and An electronic device characterized by including a storage controller configured to transmit the above response to the host device.
4. In paragraph 3, The above storage controller is, An electronic device characterized by inserting the command into the command slot and updating the storage response credit based on the host response credit.
5. In paragraph 3, The above storage controller is, An electronic device characterized by checking for empty space in the response slot based on the storage response credit, and transmitting the response and the storage command credit to the host device.
6. In paragraph 5, The above host controller is, An electronic device characterized by inserting the response into the response slot and updating the host command credit based on the storage command credit.
7. In paragraph 1, The first head pointer and the first tail pointer are referenced in the above submission queue, and The second head pointer and the second tail pointer are referenced in the above completion queue, An electronic device characterized in that the host controller stores the first head pointer, the second head pointer, the first tail pointer, and the second tail pointer.
8. In Paragraph 7, The above host controller is, An electronic device characterized by updating the first tail pointer as the command is stored in the submission queue, and updating the first head pointer as the command is transmitted to the storage device.
9. In paragraph 8, The above host controller is, An electronic device characterized by updating the second tail pointer as the response is stored in the completion queue, and updating the second head pointer as the response is executed.
10. In paragraph 1, The above at least one core includes a first core and a second core, and The above-mentioned first core processes the first submission queue and the first completion queue, and An electronic device characterized in that the above-mentioned second core processes a second submission queue and a second completion queue.
11. In Paragraph 10, The above host controller is, An electronic device characterized by transmitting the above command, the above host response credit, an SQ ID indicating a submission queue fetched to the above host controller, and a CQ ID indicating a completion queue fetched to the above host controller to the storage device.
12. In Paragraph 10, The above host controller is, An electronic device characterized by further including an arbitrator configured to select one of the first submission queue and the second submission queue and to fetch a command stored in the selected submission queue.
13. In Paragraph 10, The above host controller is, An electronic device characterized by further including a router configured to route a response stored in the response slot to a selected completion queue among the first completion queue and the second completion queue.
14. In a method of operation of a host device to which the Universal Flash Storage standard is applied, A step of writing a command to at least one submission queue; A step of transmitting to the storage device a host response credit representing the actual acceptance limit of the host device for the command and the response resulting from the execution of the command, based on a host command credit representing an estimated acceptance limit for the command of the storage device; A step of receiving a storage command credit representing the actual acceptance limit for the response and the command of the storage device; A step of updating the host command credit based on the storage command credit; and A method of operation of a host device comprising the step of writing the above response to a completion queue.
15. In Paragraph 14, The step of entering the above command is, The method includes the step of updating the tail pointer of the above submission queue, and The step of transmitting the above command and the above host response credit to the storage device is, A method of operation of a host device characterized by including the step of updating the head pointer of the above submission queue.
16. In Paragraph 14, It further includes the step of updating the head pointer of the completion queue as it performs the written response, The step of entering the above response is, A method of operation of a host device characterized by including the step of updating the tail pointer of the completion queue.
17. In Paragraph 14, The above at least one submission queue includes a first submission queue processed at a first core and a second submission queue processed at a second core, and The above at least one completion queue includes a first completion queue processed at the first core and a second completion queue processed at the second core, and The step of transmitting to the storage device above is, A method of operation of a host device characterized by including the step of further transmitting an SQ ID indicating a fetched submission queue.
18. In Paragraph 17, A method of operation of a host device further comprising the step of selecting one of the first submission queue and the second submission queue, and fetching a command stored in the selected submission queue.
19. In Paragraph 17, A method of operation of a host device further comprising the step of routing a response stored in a response slot included in the host device to a selected completion queue among the first completion queue and the second completion queue.
20. In a method of operation of a storage device to which the Universal Flash Storage standard is applied, A step of receiving a command, and a host response credit representing the actual acceptance limit of the response resulting from the execution of said command on the host device; A step of updating a storage response credit representing an estimated acceptance limit for the response of the host device based on the above host response credit; A method of operating a storage device comprising the step of transmitting a storage command credit representing the actual acceptance limit for the response and the command of the storage device.

Description

An operating method of host device and storage device using a credit The technical concept of the present disclosure relates to an electronic device that uses credits, and more specifically, to an electronic device that uses credits, and a method of operation for a host device and a storage device that interfaceive each other by using credits. Non-volatile memory can retain stored data even when the power is cut off. Recently, storage devices containing flash-based non-volatile memory, such as eMMC (embedded Multi-Media Card), UFS (Universal Flash Storage), SSD (Solid State Drive), and memory cards, are widely used, and these devices are useful for storing or transferring large amounts of data. A data processing system including a storage device may be referred to as a storage system, and the storage system may include a host device and a storage device. The host device and the storage device may be connected via various interface standards, and it is necessary to improve data processing performance by reducing the overhead of data processing operations, such as writing and reading, during interface operations. FIG. 1 is a block diagram illustrating an electronic device according to an exemplary embodiment of the present disclosure. FIG. 2 is a block diagram showing an example of an implementation of the electronic device illustrated in FIG. 1. Figure 3 is a block diagram showing an example of an implementation of an electronic device with a UFS interface applied. FIG. 4 is a diagram illustrating the process of a command being entered into a queue according to an exemplary embodiment of the present disclosure. FIG. 5a is a block diagram showing an electronic device in which a command is written according to an exemplary embodiment of the present disclosure, and FIG. 5b is a block diagram showing an electronic device in which a response is written according to an exemplary embodiment of the present disclosure. FIG. 6 is a flowchart illustrating a method of operation of an electronic device according to an exemplary embodiment of the present disclosure. FIG. 7 is a flowchart illustrating a method of operation of a host device according to an exemplary embodiment of the present disclosure. FIGS. 8a to 8c are flowcharts illustrating an embodiment of the operation method of FIG. 7. FIG. 9 is a flowchart illustrating a method of operation of a storage device according to an exemplary embodiment of the present disclosure. FIGS. 10a and FIGS. 10b are drawings illustrating the structure of a packet according to an exemplary embodiment of the present disclosure. FIG. 11 is a drawing illustrating a method of operation of a host device and a storage device according to an exemplary embodiment of the present disclosure. FIG. 12 is a block diagram showing a system to which a storage device according to an exemplary embodiment of the present disclosure is applied. FIG. 13 is a block diagram showing a UFS system according to an exemplary embodiment of the present disclosure. FIGS. 14a to 14c are drawings for illustrating the form factor of a UFS card according to an exemplary embodiment of the present disclosure. FIG. 15 is a block diagram showing a storage device according to an exemplary embodiment of the present invention. FIG. 16 is a block diagram showing a storage device according to one embodiment of the present invention. FIG. 17 is a block diagram illustrating an example of an implementation of the memory device of FIG. 16. FIG. 18 is a drawing for explaining a 3D V-NAND structure that can be applied to a UFS device according to an exemplary embodiment of the present disclosure. FIG. 19 is a drawing for explaining a BVNAND (Bonding V-NAND) structure that can be applied to a UFS device according to an exemplary embodiment of the present invention. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings. FIG. 1 is a block diagram illustrating an electronic device (10) according to an exemplary embodiment of the present disclosure. The electronic device (10) may include a host device (100) and a storage device (200). The host device (100) may issue a command (CMD) and transmit it to the storage device (200), and the storage device (200) may read, erase, or write data according to the command (CMD), and may generate a response (RESP) as a result and provide it to the host device (100). Additionally, the host device (100) may provide a response credit (CR_RESP) to the storage device (200), and the storage device (200) may provide a command credit (CR_CMD) to the host device (100). Command and response credits (CR_RESP) can be managed by being included in a command packet (PACKET_C), and response (RESP) and command credits (CR_CMD) can be managed by being included in a response packet (PACKET_R). The configuration of the packets is described in detail with reference to FIGS. 10a and 10b. The electronic device (10) may be implemented as, for example, a person