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KR-102962679-B1 - Semiconductor package with balanced wiring structure

KR102962679B1KR 102962679 B1KR102962679 B1KR 102962679B1KR-102962679-B1

Abstract

The technical concept of the present invention provides a semiconductor package having improved SI characteristics while having a chip stack structure of a plurality of semiconductor chips. The semiconductor package comprises: a package substrate; a chip stack structure mounted on the package substrate and having at least two semiconductor chips; and an external connection terminal disposed on the lower surface of the package substrate. Among the at least two semiconductor chips, a first semiconductor chip disposed at the top is connected to a first bonding pad of the package substrate through a first wire, and among the at least two semiconductor chips, a second semiconductor chip disposed below the first semiconductor chip is connected to a second bonding pad of the package substrate through a second wire. When the first bonding pad is located further from the external connection terminal than the second bonding pad, the external connection terminal is connected to the first bonding pad through wiring of the package substrate.

Inventors

  • 백기원

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260507
Application Date
20210709

Claims (10)

  1. Package substrate; A chip stack structure mounted on the above-mentioned package substrate and having at least two semiconductor chips; and Includes an external connection terminal disposed on the lower surface of the above package substrate; Among the above at least two semiconductor chips, the first semiconductor chip positioned at the top is connected to the first bonding pad of the package substrate through a first wire, and Among the above at least two semiconductor chips, the second semiconductor chip disposed below the first semiconductor chip is connected to the second bonding pad of the package substrate through a second wire, and When the first bonding pad is located further from the external connection terminal than the second bonding pad, the external connection terminal is connected to the first bonding pad through the wiring of the package substrate, and The second bonding pad is connected to the first bonding pad through upper wiring on the package substrate, and A semiconductor package having a balanced wiring structure, wherein, when viewed from the external connection terminal side, the sum of the lengths of the second wire and the upper wiring is balanced with the length of the first wire.
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  3. In Article 1, When at least one of the above at least two semiconductor chips includes a chip pad connected to an internal device layer, a connection pad connected to a wire, and a rewiring connecting the chip pad and the connection pad, A semiconductor package characterized in that the length of the rewiring is included in the calculation of the balance above.
  4. In Article 1, The first semiconductor chip is connected to the first bonding pads arranged on both sides of the package substrate in the first direction through the first wire arranged on both sides in the first direction, and The second semiconductor chip is connected to the second bonding pads arranged on both sides of the package substrate in the first direction through the second wires arranged on both sides in the first direction, and The second bonding pad is connected to the corresponding first bonding pad through upper wiring on the package substrate, and A semiconductor package characterized in that the above external connection terminal is positioned in a direction opposite to the corresponding first bonding pad with respect to the chip stacking structure.
  5. In Article 1, It further includes at least one internal semiconductor chip mounted on the package substrate, spaced apart from the chip stacking structure, and The above internal semiconductor chip is connected to a signal pad of the package substrate via a wire or bump, and When the first bonding pad is located further from the signal pad than the second bonding pad, A semiconductor package characterized in that the signal pad is connected to the first bonding pad through the wiring of the package substrate.
  6. Package substrate; A chip stacking structure mounted on the above-mentioned package substrate and having at least two semiconductor chips; and It includes at least one internal semiconductor chip mounted on the package substrate, spaced apart from the chip stacking structure; Among the above at least two semiconductor chips, the first semiconductor chip positioned at the top is connected to the first bonding pad of the package substrate through a first wire, and Among the above at least two semiconductor chips, the second semiconductor chip disposed below the first semiconductor chip is connected to the second bonding pad of the package substrate through a second wire, and The above internal semiconductor chip is connected to a signal pad of the package substrate via a wire or bump, and When the first bonding pad is located further from the signal pad than the second bonding pad, the signal pad is connected to the first bonding pad through the wiring of the package substrate, and The second bonding pad is connected to the first bonding pad through upper wiring on the package substrate, and A semiconductor package having a balanced wiring structure, in which, when viewed from the signal pad side, the sum of the lengths of the second wire and the upper wiring is balanced with the length of the first wire.
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  8. Package substrate; A chip stacking structure mounted on the above-mentioned package substrate and having at least two semiconductor chips; At least one internal semiconductor chip mounted on the package substrate, spaced apart from the chip stacking structure; and Includes an external connection terminal disposed on the lower surface of the above package substrate; Among the above at least two semiconductor chips, the first semiconductor chip positioned at the top is connected to the first bonding pad of the package substrate through a first wire, and Among the above at least two semiconductor chips, the second semiconductor chip disposed below the first semiconductor chip is connected to the second bonding pad of the package substrate through a second wire, and When the first bonding pad is located further from the external connection terminal than the second bonding pad, the external connection terminal is connected to the first bonding pad through the wiring of the package substrate, and The second bonding pad is connected to the first bonding pad through upper wiring on the package substrate, and A semiconductor package having a balanced wiring structure, wherein, when viewed from the external connection terminal side, the sum of the lengths of the second wire and the upper wiring is balanced with the length of the first wire.
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  10. In Article 8, When at least one of the above at least two semiconductor chips includes a chip pad connected to an internal device layer, a connection pad connected to a wire, and a rewiring connecting the chip pad and the connection pad, A semiconductor package characterized in that the length of the rewiring is included in the calculation of the balance above.

Description

Semiconductor package with balanced wiring structure The technical concept of the present invention relates to a semiconductor package, and in particular, to a semiconductor package having a chip stacking structure of a plurality of semiconductor chips mounted on a package substrate. Driven by the rapid advancement of the electronics industry and user demands, electronic devices are becoming increasingly smaller and lighter. Consequently, the semiconductor packages used in these devices are also becoming smaller and lighter; furthermore, high reliability is required for these packages alongside high performance and high capacity. For instance, regarding semiconductor package reliability, the miniaturization and increased operating speeds of packages are leading to issues with signal integrity (SI) degradation caused by noise. Accordingly, research and development on package structures capable of resolving this SI degradation problem are continuously being conducted. FIGS. 1a and FIGS. 1b are a perspective view and a cross-sectional view of a semiconductor package having a balanced wiring structure according to an embodiment of the present invention, and FIG. 1c is a conceptual diagram for explaining the balanced wiring structure in the semiconductor package of FIG. 1a. FIGS. 2a to 2d are cross-sectional views of a semiconductor package having a balanced wiring structure according to embodiments of the present invention. FIGS. 3a and 3b are cross-sectional views of a semiconductor package having a balanced wiring structure according to embodiments of the present invention. FIGS. 4a to 4c are cross-sectional views of a semiconductor package having a balanced wiring structure according to embodiments of the present invention. FIGS. 5a and 5b are cross-sectional views of a semiconductor package having a balanced wiring structure according to embodiments of the present invention. FIGS. 6a to 6c are simulation photos and graphs showing a comparison of the SI characteristics of a conventional semiconductor package and a semiconductor package of the present embodiment. FIGS. 7a and 7b are a perspective view and a cross-sectional view of a semiconductor package having a balanced wiring structure according to one embodiment of the present invention. FIG. 8 is a cross-sectional view of a semiconductor package having a balanced wiring structure according to an embodiment of the present invention. Embodiments of the present invention will be described in detail below with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted. FIGS. 1a and FIGS. 1b are a perspective view and a cross-sectional view of a semiconductor package having a balanced wiring structure according to an embodiment of the present invention, and FIG. 1c is a conceptual diagram for explaining the balanced wiring structure in the semiconductor package of FIG. 1a. Referring to FIG. 1a and FIG. 1b, a semiconductor package (1000, hereinafter simply referred to as a "semiconductor package") having a balanced wiring structure of the present embodiment may include a package substrate (100), a chip stack structure (200), and an external connection terminal (300). The package substrate (100) may include a body layer (101), a bonding pad (110), wiring (120), and an external pad (130). The body layer (101) can be formed from various materials. For example, the body layer (101) can be formed from silicon, ceramic, organic material, glass, epoxy resin, etc., depending on the type of package substrate (100). In the semiconductor package (1000) of the present embodiment, the package substrate (100) may be a printed circuit board (PCB), and the body layer (101) may be based on epoxy resin. The body layer (101) may be formed as a single layer or multiple layers corresponding to the wiring (120). For example, when the wiring (120) is placed inside the body layer (101), the body layer (101) may include one more layer than the layer of the wiring (120) placed inside. However, according to an embodiment, if the wiring (120) is not disposed inside the body layer (101) but is formed only on the upper and/or lower surface of the body layer (101), the body layer (101) may be formed as a single layer. Although not illustrated, a protective layer may be disposed on the lower and upper surfaces of the body layer (101). The protective layer may cover and protect the wiring (120) disposed on the upper and lower surfaces of the body layer (101). The protective layer may be formed, for example, as a solder resist (SR). However, the material of the protective layer is not limited to SR. For example, depending on the type or function of the substrate, the protective layer may be formed as a passivation layer such as an oxide film or a nitride film. Meanwhile, the bonding pad (110) on the upper surface of the body layer (101) and the external pad (130) on the lower surface may be