KR-102962681-B1 - Memory device and method for controlling row hammer

Abstract

A row hammer control method and a memory device are disclosed. The memory device promotes a fake entry whose access count is greater than or equal to a first threshold to a real entry, adjusts the ratio of a first entry space allocated to a real entry in an address table and a second entry space allocated to a fake entry based on the number of times a fake entry is evicted from an address register, and selectively evicts less intensive row hammer addresses.

Inventors

• 류정민

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20211026

Claims (20)

1. In a memory device, A memory cell array comprising a plurality of memory cell rows; A control logic circuit that distinguishes access addresses for the memory cell array into real entries and fake entries, manages an address register including a bit identifier corresponding to each of the access addresses, wherein the bit identifier indicates whether the access address is a real entry or a fake entry, and identifies a row hammer address among the access addresses. The above genuine entry represents an access address having an access count greater than or equal to a first threshold, and The above fake entry represents an access address having an access count less than the first threshold; and It includes a refresh control circuit that refreshes a memory cell row physically adjacent to the memory cell row associated with the row hammer address during a row hammer monitoring time frame, and The above control logic circuit is a memory device that promotes the fake entry to the real entry when the number of accesses to the fake entry exceeds the first threshold.
2. In paragraph 1, The above control logic circuit includes an address register that stores the monitored access addresses, and The above address register is, An address storage unit that stores the bit identifier for each of the above access addresses, distinguishing between the real entry and the fake entry; and A memory device comprising a counter storage unit that stores the number of accesses to each of the real entry and the fake entry.
3. In paragraph 2, The above control logic circuit is a memory device that stores the above-mentioned false entry in a first entry space allocated to the above-mentioned real entry within the above-mentioned address register.
4. In paragraph 3, The above control logic circuit is a memory device that swaps the real entry having the lowest access count stored in the address register with the promoted fake entry when there is no empty space in the first entry space.
5. In paragraph 4, A memory device in which the control logic circuit demotes the real entry having the lowest access count to the fake entry, and initializes the access count value of the demoted real entry to a first value smaller than the first threshold.
6. In paragraph 5, A memory device in which the first value is one less than the threshold value.
7. In paragraph 1, The above control logic circuit is a memory device that initializes the access count value of the real entry corresponding to the refreshed row hammer address to the first threshold.
8. In paragraph 1, The above control logic circuit is a memory device that uses the basic refresh rate time (tREFi) specified in the memory device as the low hammer monitoring time frame.
9. In a memory device, A memory cell array comprising a plurality of memory cell rows; A control logic circuit that distinguishes access addresses for the memory cell array into real entries and fake entries, and identifies a row hammer address among the access addresses, The above genuine entry represents an access address having an access count greater than or equal to a first threshold, and The above fake entry represents an access address having an access count less than the first threshold; and It includes a refresh control circuit that refreshes a memory cell row physically adjacent to the memory cell row associated with the row hammer address during a row hammer monitoring time frame, and The above control logic circuit is a memory device that stores the number of times the fake entry is ejected and adjusts the ratio of the first entry space allocated to the real entry and the second entry space allocated to the fake entry based on the number of times the fake entry is ejected.
10. In Paragraph 9, The above control logic circuit includes an address register that stores the monitored access addresses, and The above address register is, An address storage unit that stores the real entry and the fake entry by marking a bit identifier for each of the above access addresses; and A memory device comprising a counter storage unit that stores the number of accesses to each of the real entry and the fake entry.
11. In Paragraph 10, A memory device in which the above control logic circuit receives a first access address and stores the first access address as a first fake entry in the second entry space allocated within the address register.
12. In Paragraph 11, A memory device in which, if there is no empty space in the second entry space, the control logic circuit ejects the second fake entry having the lowest access count stored in the address register from the address register, stores the first fake entry in the place of the ejected second fake entry, and increases the ejection count by 1.
13. In Paragraph 12, The above control logic circuit is a memory device that initializes the access count of the first fake entry stored in the address register to 1.
14. In Paragraph 11, The above control logic circuit is a memory device that increases the access counter value of the first fake entry by 1 if the first fake entry matches the fake entry stored in the address register.
15. In Paragraph 10, A memory device that stores a first ejection count during a previous row hammer monitoring time frame and adjusts the ratio of the first entry space and the second entry space allocated to the address register by comparing the first ejection count with the second ejection count during the current row hammer monitoring time frame.
16. In paragraph 15, The above control logic circuit is a memory device that shrinks by reducing the first entry space when the second ejection count is greater than the first ejection count.
17. In Paragraph 16, The above control logic circuit is a memory device that decreases the first entry space by 1 when the first entry space is greater than the minimum entry value allocated to the address register.
18. In paragraph 15, The above control logic circuit is a memory device that expands by increasing the first entry space when the second ejection count is smaller than the first ejection count.
19. In Paragraph 16, The above control logic circuit is a memory device that increases the first entry space by 1 when the first entry space is smaller than the maximum entry value allocated to the address register.
20. In Paragraph 9, The above control logic circuit is a memory device that initializes the access count value of the real entry corresponding to the refreshed row hammer address to the first threshold.

Description

Memory device and method for controlling row hammer The present invention relates to semiconductor memory devices, and more specifically, to a memory device that controls a row hammer using an entry identifier that distinguishes between a fake entry and a real entry, and a method of operating the same. Systems using semiconductor chips widely utilize Dynamic Random Access Memory (DRAM) as operational memory or main memory to store data or instructions used by a host within the system and/or to perform computational operations. Generally, DRAM writes data or reads out written data under the control of the host. When performing computational operations, the host retrieves instructions and/or data from DRAM and uses the data to execute instructions and/or perform computational operations. If the result of a computational operation exists, the host writes the result of the computational operation back to DRAM. DRAM cell sizes are decreasing to increase DRAM capacity and density. Some DRAM-based systems experience intermittent failures due to heavy workloads. These failures are traced to repetitive access to a single memory cell row, also known as row hammer. Memory cells connected to physically adjacent memory cell rows are disturbed by row hammer, which can lead to data corruption. Memory cells affected by row hammer can be refreshed by a target row refresh operation. To manage row hammers, the DRAM can monitor hammer address(s) that are intensively accessed among access addresses for a certain period of time. The DRAM stores the hammer address(s) in limited registers of the address storage unit, generates hammer refresh address(s) based on the hammer address(s) representing the addresses of memory cell row(s) that are physically adjacent to the memory cell row(s) corresponding to the hammer address(s), and can target refresh the memory cells connected to the memory cell row corresponding to the hammer refresh address. However, an aggressor can use fake entry(s) to lure a row hammer with the intent of disrupting the row hammer management operations of the DRAM. As fake entry(s) are newly stored in the limited registers of the address storage unit, the hammer address(s) stored in the registers are evicted, and monitored row hammer information may be lost. The evicted hammer address has the problem of becoming vulnerable to the row hammer. Accordingly, countermeasures are required against a hacker pattern of Rowhammer attack that maliciously extracts Rowhammer addresses from the address storage unit to induce Rowhammer information to be lost. FIG. 1 is a drawing illustrating a system including a memory device for controlling a row hammer according to exemplary embodiments of the present invention. FIG. 2 is a block diagram illustrating a memory device according to embodiments of the present invention. FIG. 3 is a block diagram illustrating a row hammer control circuit according to embodiments of the present invention. Figure 4 is a diagram illustrating the refresh operation of the memory device of Figure 2. Figure 5 is a diagram conceptually illustrating an example of how the address table of Figure 3 is reconfigured. FIG. 6 is a flow diagram illustrating the operation of a control logic circuit according to embodiments of the present invention. FIG. 7 is a flow diagram illustrating the operation of a control logic circuit according to embodiments of the present invention. FIGS. 8 to 12 are drawings showing an address table that is reconstructed according to the operation flows of FIGS. 6 and 7. FIG. 13 is a flow diagram illustrating the operation of a control logic circuit according to embodiments of the present invention. FIG. 14 is a block diagram showing a system including a memory device for controlling a row hammer according to embodiments of the present invention. FIG. 1 is a diagram illustrating a system including a memory device for controlling a row hammer according to exemplary embodiments of the present invention. Referring to FIG. 1, the system (100) may include a host device (110) and a memory device (120). The host device (110) may be communicatively connected to the memory device (120) through a memory bus (130). The host device (110) may be, for example, a computing system such as a computer, laptop, server, workstation, portable communication terminal, PDA (Personal Digital Assistant), PMP (Portable Multimedia Player), smartphone, or wearable device. Or the host device (110) may be some of the components included in a computing system such as a graphics card. The host device (110) is a functional block that performs general computer operations within the system (100) and may correspond to a Central Processing Unit (CPU), a Digital Signal Processor (DSP), a Graphics Processing Unit (GPU), or an Application Processor (AP). The host device (110) may include a memory controller (112) that manages the transmission and reception of data to and from a memory device (120). A memory controller (112) can