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KR-102962682-B1 - Cell comprising individual source regions, and integrated circuit comprising the same cell

KR102962682B1KR 102962682 B1KR102962682 B1KR 102962682B1KR-102962682-B1

Abstract

The technical concept of the present invention provides a cell having a structure capable of improving the performance of the cell without additional process development, and an integrated circuit including the cell. The cell comprises active regions each extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; gate lines extending across the active regions in the second direction and spaced apart from each other in the first direction; first contacts disposed on both sides of each of the gate lines in the first direction and connected to the active regions; metal lines disposed above the gate lines and the first contacts, extending in the first direction and spaced apart from each other in the second direction; and second contacts connecting the gate lines to the metal lines. and vias connecting the first contacts to the metal lines; wherein two gate lines adjacent to each other in the first direction have a first gap or a second gap larger than the first gap, and a source separation structure extending in the second direction is disposed between two gate lines adjacent by the second gap, and individual source regions corresponding to each of the two gate lines are formed in the active regions by the source separation structure.

Inventors

  • 김윤진
  • 박판제
  • 천관영

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260507
Application Date
20211028

Claims (10)

  1. Active regions each extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; Gate lines extending across the active regions in the second direction and spaced apart from each other in the first direction; First contacts disposed on both sides of each of the gate lines in the first direction and connected to the active regions; Metal lines disposed above the gate lines and first contacts, extending in the first direction and spaced apart from each other in the second direction; Second contacts connecting the gate lines to the metal lines; and vias connecting the first contacts to the metal lines; comprising The two gate lines adjacent to each other in the first direction have a first gap, or a second gap larger than the first gap, and A source separation structure extending in the second direction is disposed between two gate lines adjacent to the second interval, and individual source regions corresponding to each of the two gate lines are formed in the active regions by the source separation structure. The first contact is distinguished into individual contacts connected to each of the active regions and a common contact connected to the active regions in common, and The above individual contacts are placed in the above individual source regions, and The above common contact is disposed in the drain region opposite to the individual source region for each of the two gate lines, A cell containing an individual source area.
  2. In Article 1, The above cell is separated from adjacent cells through a Single Diffusion Break (SDB) structure positioned on both outer parts in the first direction, and The source separation structure has a spacing substantially equal to the first spacing and each of the two gate lines, and The above source separation structure is a cell comprising individual source regions characterized by having the above SDB structure.
  3. In Article 1, The cell comprises individual source regions characterized in that the cell is a standard cell in which four of an inverter, NAND, and NOR are connected in a parallel structure.
  4. In Article 1, The above cell is a standard cell including an inverter, and The above active regions include an upper first active region and a lower second active region in the second direction, and Each of the four gate lines crosses the first and second active regions, and The source separation structure is positioned between the second and third gate lines from the left in the first direction, and separates each of the first and second active regions into two regions, and The above cell has a line-symmetric structure with respect to the source separation structure as an axis, and In the first direction, the first contact is disposed on each of the first and second active regions, to the left of the first gate line and between the second gate line and the source separation structure. A cell comprising individual source regions characterized by having a first contact disposed in common to the first and second active regions between the first and second gate lines on the left in the first direction.
  5. In Article 1, The above cell is a standard cell including NAND, and The above active regions include an upper first active region and a lower second active region in the second direction, and Each of the eight gate lines crosses the first and second active regions, and The source separation structure is positioned between the second and third gate lines from the left in the first direction and between the sixth and seventh gate lines, and separates each of the first and second active regions into three regions, and The cell has a line-symmetric structure with respect to the first contact disposed in each of the first and second active regions between the fourth and fifth gate lines from the left in the first direction, and In the first direction, the first contact is disposed in each of the first and second active regions, to the left of the first gate line, between the first and second gate lines, and between the second gate line and the first source separation structure. The first contact disposed in the second active region to the left of the first gate line in the first direction is connected to the first contact disposed in the first active region to the right through the vias and metal lines, and A cell comprising an individual source region, characterized in that the first contact disposed in the first active region to the left of the fourth gate line from the left in the first direction is connected to the first contact disposed in the second active region to the right through the vias and metal lines.
  6. In Article 1, The above cell is a standard cell containing NOR, and The metal lines include an uppermost power line, a lowermost ground line, and intermediate lines positioned between the power line and the ground line in the second direction, and A cell comprising individual source regions characterized in that the active regions, gate lines, first contacts, second contacts, and vias of the cell have a mirror-symmetric structure with respect to the active regions, gate lines, first contacts, second contacts, and vias of the NAND cell in the second direction.
  7. It includes cells arranged along a first direction and a second direction perpendicular to the first direction, and The above cell is, Active regions each extending in a first direction and spaced apart from each other in the second direction; Gate lines extending across the active regions in the second direction and spaced apart from each other in the first direction; First contacts disposed on both sides of each of the gate lines in the first direction and connected to the active regions; Metal lines disposed above the gate lines and first contacts, extending in the first direction and spaced apart from each other in the second direction; Second contacts connecting the gate lines to the metal lines; and vias connecting the first contacts to the metal lines; comprising, The two gate lines adjacent to each other in the first direction have a first gap, or a second gap larger than the first gap, and A source separation structure extending in the second direction is disposed between two gate lines adjacent to the second interval, and individual source regions corresponding to each of the two gate lines are formed in the active regions by the source separation structure. The first contact is distinguished into individual contacts connected to each of the active regions and a common contact connected to the active regions in common, and The above individual contacts are placed in the above individual source regions, and The above common contact is disposed in the drain region opposite to the individual source region for each of the two gate lines, integrated circuit.
  8. In Article 7, The above cell is separated from adjacent cells through an SDB structure disposed on both outer parts in the first direction, and The source separation structure has a spacing substantially equal to the first spacing and each of the two gate lines, and An integrated circuit characterized by the above source isolation structure having the above SDB structure.
  9. Cells are arranged along a first direction and a second direction perpendicular to the first direction, and include cells separated from each other through an SDB structure along the first direction. The above cell is, First and second active regions each extending in a first direction and spaced apart from each other in the second direction; Gate lines extending across the first and second active regions in the second direction and spaced apart from each other in the first direction; First contacts disposed on both sides of each of the gate lines in the first direction and connected to the first and second active regions; and Metal lines disposed above the gate lines, extending in the first direction and spaced apart from each other in the second direction; comprising, The two gate lines adjacent to each other in the first direction have a first gap, or a second gap that is twice the first gap, and A source separation structure extending in the second direction is disposed between two gate lines adjacent to the second interval, and individual source regions corresponding to each of the two gate lines are formed in the first and second active regions by the source separation structure. The first contact is distinguished into individual contacts connected to each of the first and second active regions and a common contact connected to the first and second active regions in common, and The above individual contacts are placed in the above individual source regions, and The above common contact is disposed in the drain region opposite to the individual source region for each of the two gate lines, integrated circuit.
  10. In Article 9, The first and second active regions above constitute any one of a planar FET, a pin FET, and an MBC FET, and An integrated circuit characterized in that the cell is a standard cell in which four of an inverter, a NAND, and a NOR are connected in a parallel structure.

Description

A cell comprising individual source regions, and an integrated circuit comprising the same cell The technical concept of the present invention relates to an integrated circuit, and in particular to an integrated circuit based on a standard cell. Integrated circuits can be designed based on cells, such as standard cells. Specifically, the layout of an integrated circuit can be generated by arranging standard cells according to data defining the integrated circuit and routing the arranged standard cells. Recently, the configuration of integrated circuits has become more complex, and semiconductor manufacturing processes are becoming extremely miniaturized. As semiconductor manufacturing processes become miniaturized, standard cells not only contain reduced-size patterns across multiple layers, but the size of the standard cells themselves is also decreasing. Consequently, the difficulty of the integrated circuit process is increasing, and it is also reaching limits in terms of performance improvement. FIGS. 1A and FIGS. 1B are layouts of a cell including an individual source region according to one embodiment of the present invention and a cell of a comparative example. FIGS. 2a and FIGS. 2b are cross-sectional views showing the II' portion of the cell in FIG. 1a and the II-II' portion of the cell in FIG. 1b, respectively. FIGS. 3a to 3c are cross-sectional views showing various structures of the active region in the cell of FIG. 1a. Figures 4a and 4b are layouts of cells to explain the difference between the Double Diffusion Break (DDB) structure and the Single Diffusion Break (SDB) structure. FIGS. 5a to 5c are circuit diagrams, layouts, and cross-sectional views relating to a cell including individual source regions according to one embodiment of the present invention. FIGS. 6a and 6b are circuit diagrams and layouts related to a cell including individual source regions according to one embodiment of the present invention. FIGS. 7a and 7b are circuit diagrams and layouts related to a cell including individual source regions according to one embodiment of the present invention. Embodiments of the present invention will be described in detail below with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted. FIGS. 1a and 1b are layouts of a cell including an individual source region according to one embodiment of the present invention and a cell of a comparative example, and FIGS. 2a and 2b are cross-sectional views showing the I-I' portion of the cell in FIG. 1a and the II-II' portion of the cell in FIG. 1b, respectively. Referring to FIGS. 1a to 2b, a cell (100, hereinafter simply referred to as 'cell') including individual source regions of the present embodiment may include a semiconductor substrate (101), active regions (110), gate lines (120), first contacts (130), metal lines (140), second contacts (150), vias (160), and a source separation structure (170). The semiconductor substrate (101) may include silicon (Si), such as single-crystal silicon, polycrystalline silicon, or amorphous silicon. However, the material of the semiconductor substrate (101) is not limited to silicon. For example, in some embodiments, the semiconductor substrate (101) may include a group IV semiconductor such as germanium (Ge), a group IV-IV compound semiconductor such as silicon germanium (SiGe) or silicon carbide (SiC), or a group III-V compound semiconductor such as gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). Active regions (110) may be formed on a semiconductor substrate (101). The active regions (110) may extend in a first direction (x direction) and be spaced apart from each other in a second direction (y direction). In the second direction (y direction), the upper active region (110) and the lower active region (110) may be separated by a device isolation layer (115), such as Deep Trench Isolation (DTI). The device isolation layer (115) may include, for example, an oxide, a nitride, or an oxynitride. In the cell (100) of the present embodiment, the upper active region (110) in the second direction (y direction) may be a PMOS region, and the lower active region (110) may be an NMOS region. In other words, the upper active region (110) can form PMOS transistors together with gate lines (120), and the lower active region (110) can form NMOS transistors together with gate lines (120). The active regions (110) may include a source region (112) and a drain region (114), which are high-concentration doping regions disposed on both sides of each of the gate lines (120) in the first direction (x direction), and a channel region (116) between the source region (112) and the drain region (114). Meanwhile, the active regions (110) may have various structures and may form transistors of various structures. For example, the active regions (110) may form a planar FET (Field Effect Transistor),